__  __    __   __  _____      _            _          _____ _          _ _ 
 |  \/  |   \ \ / / |  __ \    (_)          | |        / ____| |        | | |
 | \  / |_ __\ V /  | |__) | __ ___   ____ _| |_ ___  | (___ | |__   ___| | |
 | |\/| | '__|> <   |  ___/ '__| \ \ / / _` | __/ _ \  \___ \| '_ \ / _ \ | |
 | |  | | |_ / . \  | |   | |  | |\ V / (_| | ||  __/  ____) | | | |  __/ | |
 |_|  |_|_(_)_/ \_\ |_|   |_|  |_| \_/ \__,_|\__\___| |_____/|_| |_|\___V 2.1
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/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Lochnagar2 register definitions
 *
 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
 *                         Cirrus Logic International Semiconductor Ltd.
 *
 * Author: Charles Keepax <[email protected]>
 */

#ifndef LOCHNAGAR2_REGISTERS_H
#define LOCHNAGAR2_REGISTERS_H

/* Register Addresses */
#define LOCHNAGAR2_CDC_AIF1_CTRL                      0x000D
#define LOCHNAGAR2_CDC_AIF2_CTRL                      0x000E
#define LOCHNAGAR2_CDC_AIF3_CTRL                      0x000F
#define LOCHNAGAR2_DSP_AIF1_CTRL                      0x0010
#define LOCHNAGAR2_DSP_AIF2_CTRL                      0x0011
#define LOCHNAGAR2_PSIA1_CTRL                         0x0012
#define LOCHNAGAR2_PSIA2_CTRL                         0x0013
#define LOCHNAGAR2_GF_AIF3_CTRL                       0x0014
#define LOCHNAGAR2_GF_AIF4_CTRL                       0x0015
#define LOCHNAGAR2_GF_AIF1_CTRL                       0x0016
#define LOCHNAGAR2_GF_AIF2_CTRL                       0x0017
#define LOCHNAGAR2_SPDIF_AIF_CTRL                     0x0018
#define LOCHNAGAR2_USB_AIF1_CTRL                      0x0019
#define LOCHNAGAR2_USB_AIF2_CTRL                      0x001A
#define LOCHNAGAR2_ADAT_AIF_CTRL                      0x001B
#define LOCHNAGAR2_CDC_MCLK1_CTRL                     0x001E
#define LOCHNAGAR2_CDC_MCLK2_CTRL                     0x001F
#define LOCHNAGAR2_DSP_CLKIN_CTRL                     0x0020
#define LOCHNAGAR2_PSIA1_MCLK_CTRL                    0x0021
#define LOCHNAGAR2_PSIA2_MCLK_CTRL                    0x0022
#define LOCHNAGAR2_SPDIF_MCLK_CTRL                    0x0023
#define LOCHNAGAR2_GF_CLKOUT1_CTRL                    0x0024
#define LOCHNAGAR2_GF_CLKOUT2_CTRL                    0x0025
#define LOCHNAGAR2_ADAT_MCLK_CTRL                     0x0026
#define LOCHNAGAR2_SOUNDCARD_MCLK_CTRL                0x0027
#define LOCHNAGAR2_GPIO_FPGA_GPIO1                    0x0031
#define LOCHNAGAR2_GPIO_FPGA_GPIO2                    0x0032
#define LOCHNAGAR2_GPIO_FPGA_GPIO3                    0x0033
#define LOCHNAGAR2_GPIO_FPGA_GPIO4                    0x0034
#define LOCHNAGAR2_GPIO_FPGA_GPIO5                    0x0035
#define LOCHNAGAR2_GPIO_FPGA_GPIO6                    0x0036
#define LOCHNAGAR2_GPIO_CDC_GPIO1                     0x0037
#define LOCHNAGAR2_GPIO_CDC_GPIO2                     0x0038
#define LOCHNAGAR2_GPIO_CDC_GPIO3                     0x0039
#define LOCHNAGAR2_GPIO_CDC_GPIO4                     0x003A
#define LOCHNAGAR2_GPIO_CDC_GPIO5                     0x003B
#define LOCHNAGAR2_GPIO_CDC_GPIO6                     0x003C
#define LOCHNAGAR2_GPIO_CDC_GPIO7                     0x003D
#define LOCHNAGAR2_GPIO_CDC_GPIO8                     0x003E
#define LOCHNAGAR2_GPIO_DSP_GPIO1                     0x003F
#define LOCHNAGAR2_GPIO_DSP_GPIO2                     0x0040
#define LOCHNAGAR2_GPIO_DSP_GPIO3                     0x0041
#define LOCHNAGAR2_GPIO_DSP_GPIO4                     0x0042
#define LOCHNAGAR2_GPIO_DSP_GPIO5                     0x0043
#define LOCHNAGAR2_GPIO_DSP_GPIO6                     0x0044
#define LOCHNAGAR2_GPIO_GF_GPIO2                      0x0045
#define LOCHNAGAR2_GPIO_GF_GPIO3                      0x0046
#define LOCHNAGAR2_GPIO_GF_GPIO7                      0x0047
#define LOCHNAGAR2_GPIO_CDC_AIF1_BCLK                 0x0048
#define LOCHNAGAR2_GPIO_CDC_AIF1_RXDAT                0x0049
#define LOCHNAGAR2_GPIO_CDC_AIF1_LRCLK                0x004A
#define LOCHNAGAR2_GPIO_CDC_AIF1_TXDAT                0x004B
#define LOCHNAGAR2_GPIO_CDC_AIF2_BCLK                 0x004C
#define LOCHNAGAR2_GPIO_CDC_AIF2_RXDAT                0x004D
#define LOCHNAGAR2_GPIO_CDC_AIF2_LRCLK                0x004E
#define LOCHNAGAR2_GPIO_CDC_AIF2_TXDAT                0x004F
#define LOCHNAGAR2_GPIO_CDC_AIF3_BCLK                 0x0050
#define LOCHNAGAR2_GPIO_CDC_AIF3_RXDAT                0x0051
#define LOCHNAGAR2_GPIO_CDC_AIF3_LRCLK                0x0052
#define LOCHNAGAR2_GPIO_CDC_AIF3_TXDAT                0x0053
#define LOCHNAGAR2_GPIO_DSP_AIF1_BCLK                 0x0054
#define LOCHNAGAR2_GPIO_DSP_AIF1_RXDAT                0x0055
#define LOCHNAGAR2_GPIO_DSP_AIF1_LRCLK                0x0056
#define LOCHNAGAR2_GPIO_DSP_AIF1_TXDAT                0x0057
#define LOCHNAGAR2_GPIO_DSP_AIF2_BCLK                 0x0058
#define LOCHNAGAR2_GPIO_DSP_AIF2_RXDAT                0x0059
#define LOCHNAGAR2_GPIO_DSP_AIF2_LRCLK                0x005A
#define LOCHNAGAR2_GPIO_DSP_AIF2_TXDAT                0x005B
#define LOCHNAGAR2_GPIO_PSIA1_BCLK                    0x005C
#define LOCHNAGAR2_GPIO_PSIA1_RXDAT                   0x005D
#define LOCHNAGAR2_GPIO_PSIA1_LRCLK                   0x005E
#define LOCHNAGAR2_GPIO_PSIA1_TXDAT                   0x005F
#define LOCHNAGAR2_GPIO_PSIA2_BCLK                    0x0060
#define LOCHNAGAR2_GPIO_PSIA2_RXDAT                   0x0061
#define LOCHNAGAR2_GPIO_PSIA2_LRCLK                   0x0062
#define LOCHNAGAR2_GPIO_PSIA2_TXDAT                   0x0063
#define LOCHNAGAR2_GPIO_GF_AIF3_BCLK                  0x0064
#define LOCHNAGAR2_GPIO_GF_AIF3_RXDAT                 0x0065
#define LOCHNAGAR2_GPIO_GF_AIF3_LRCLK                 0x0066
#define LOCHNAGAR2_GPIO_GF_AIF3_TXDAT                 0x0067
#define LOCHNAGAR2_GPIO_GF_AIF4_BCLK                  0x0068
#define LOCHNAGAR2_GPIO_GF_AIF4_RXDAT                 0x0069
#define LOCHNAGAR2_GPIO_GF_AIF4_LRCLK                 0x006A
#define LOCHNAGAR2_GPIO_GF_AIF4_TXDAT                 0x006B
#define LOCHNAGAR2_GPIO_GF_AIF1_BCLK                  0x006C
#define LOCHNAGAR2_GPIO_GF_AIF1_RXDAT                 0x006D
#define LOCHNAGAR2_GPIO_GF_AIF1_LRCLK                 0x006E
#define LOCHNAGAR2_GPIO_GF_AIF1_TXDAT                 0x006F
#define LOCHNAGAR2_GPIO_GF_AIF2_BCLK                  0x0070
#define LOCHNAGAR2_GPIO_GF_AIF2_RXDAT                 0x0071
#define LOCHNAGAR2_GPIO_GF_AIF2_LRCLK                 0x0072
#define LOCHNAGAR2_GPIO_GF_AIF2_TXDAT                 0x0073
#define LOCHNAGAR2_GPIO_DSP_UART1_RX                  0x0074
#define LOCHNAGAR2_GPIO_DSP_UART1_TX                  0x0075
#define LOCHNAGAR2_GPIO_DSP_UART2_RX                  0x0076
#define LOCHNAGAR2_GPIO_DSP_UART2_TX                  0x0077
#define LOCHNAGAR2_GPIO_GF_UART2_RX                   0x0078
#define LOCHNAGAR2_GPIO_GF_UART2_TX                   0x0079
#define LOCHNAGAR2_GPIO_USB_UART_RX                   0x007A
#define LOCHNAGAR2_GPIO_CDC_PDMCLK1                   0x007C
#define LOCHNAGAR2_GPIO_CDC_PDMDAT1                   0x007D
#define LOCHNAGAR2_GPIO_CDC_PDMCLK2                   0x007E
#define LOCHNAGAR2_GPIO_CDC_PDMDAT2                   0x007F
#define LOCHNAGAR2_GPIO_CDC_DMICCLK1                  0x0080
#define LOCHNAGAR2_GPIO_CDC_DMICDAT1                  0x0081
#define LOCHNAGAR2_GPIO_CDC_DMICCLK2                  0x0082
#define LOCHNAGAR2_GPIO_CDC_DMICDAT2                  0x0083
#define LOCHNAGAR2_GPIO_CDC_DMICCLK3                  0x0084
#define LOCHNAGAR2_GPIO_CDC_DMICDAT3                  0x0085
#define LOCHNAGAR2_GPIO_CDC_DMICCLK4                  0x0086
#define LOCHNAGAR2_GPIO_CDC_DMICDAT4                  0x0087
#define LOCHNAGAR2_GPIO_DSP_DMICCLK1                  0x0088
#define LOCHNAGAR2_GPIO_DSP_DMICDAT1                  0x0089
#define LOCHNAGAR2_GPIO_DSP_DMICCLK2                  0x008A
#define LOCHNAGAR2_GPIO_DSP_DMICDAT2                  0x008B
#define LOCHNAGAR2_GPIO_I2C2_SCL                      0x008C
#define LOCHNAGAR2_GPIO_I2C2_SDA                      0x008D
#define LOCHNAGAR2_GPIO_I2C3_SCL                      0x008E
#define LOCHNAGAR2_GPIO_I2C3_SDA                      0x008F
#define LOCHNAGAR2_GPIO_I2C4_SCL                      0x0090
#define LOCHNAGAR2_GPIO_I2C4_SDA                      0x0091
#define LOCHNAGAR2_GPIO_DSP_STANDBY                   0x0092
#define LOCHNAGAR2_GPIO_CDC_MCLK1                     0x0093
#define LOCHNAGAR2_GPIO_CDC_MCLK2                     0x0094
#define LOCHNAGAR2_GPIO_DSP_CLKIN                     0x0095
#define LOCHNAGAR2_GPIO_PSIA1_MCLK                    0x0096
#define LOCHNAGAR2_GPIO_PSIA2_MCLK                    0x0097
#define LOCHNAGAR2_GPIO_GF_GPIO1                      0x0098
#define LOCHNAGAR2_GPIO_GF_GPIO5                      0x0099
#define LOCHNAGAR2_GPIO_DSP_GPIO20                    0x009A
#define LOCHNAGAR2_GPIO_CHANNEL1                      0x00B9
#define LOCHNAGAR2_GPIO_CHANNEL2                      0x00BA
#define LOCHNAGAR2_GPIO_CHANNEL3                      0x00BB
#define LOCHNAGAR2_GPIO_CHANNEL4                      0x00BC
#define LOCHNAGAR2_GPIO_CHANNEL5                      0x00BD
#define LOCHNAGAR2_GPIO_CHANNEL6                      0x00BE
#define LOCHNAGAR2_GPIO_CHANNEL7                      0x00BF
#define LOCHNAGAR2_GPIO_CHANNEL8                      0x00C0
#define LOCHNAGAR2_GPIO_CHANNEL9                      0x00C1
#define LOCHNAGAR2_GPIO_CHANNEL10                     0x00C2
#define LOCHNAGAR2_GPIO_CHANNEL11                     0x00C3
#define LOCHNAGAR2_GPIO_CHANNEL12                     0x00C4
#define LOCHNAGAR2_GPIO_CHANNEL13                     0x00C5
#define LOCHNAGAR2_GPIO_CHANNEL14                     0x00C6
#define LOCHNAGAR2_GPIO_CHANNEL15                     0x00C7
#define LOCHNAGAR2_GPIO_CHANNEL16                     0x00C8
#define LOCHNAGAR2_MINICARD_RESETS                    0x00DF
#define LOCHNAGAR2_ANALOGUE_PATH_CTRL1                0x00E3
#define LOCHNAGAR2_ANALOGUE_PATH_CTRL2                0x00E4
#define LOCHNAGAR2_COMMS_CTRL4                        0x00F0
#define LOCHNAGAR2_SPDIF_CTRL                         0x00FE
#define LOCHNAGAR2_IMON_CTRL1                         0x0108
#define LOCHNAGAR2_IMON_CTRL2                         0x0109
#define LOCHNAGAR2_IMON_CTRL3                         0x010A
#define LOCHNAGAR2_IMON_CTRL4                         0x010B
#define LOCHNAGAR2_IMON_DATA1                         0x010C
#define LOCHNAGAR2_IMON_DATA2                         0x010D
#define LOCHNAGAR2_POWER_CTRL                         0x0116
#define LOCHNAGAR2_MICVDD_CTRL1                       0x0119
#define LOCHNAGAR2_MICVDD_CTRL2                       0x011B
#define LOCHNAGAR2_VDDCORE_CDC_CTRL1                  0x011E
#define LOCHNAGAR2_VDDCORE_CDC_CTRL2                  0x0120
#define LOCHNAGAR2_SOUNDCARD_AIF_CTRL                 0x0180

/* (0x000D-0x001B, 0x0180)  CDC_AIF1_CTRL - SOUNCARD_AIF_CTRL */
#define LOCHNAGAR2_AIF_ENA_MASK                       0x8000
#define LOCHNAGAR2_AIF_ENA_SHIFT                          15
#define LOCHNAGAR2_AIF_LRCLK_DIR_MASK                 0x4000
#define LOCHNAGAR2_AIF_LRCLK_DIR_SHIFT                    14
#define LOCHNAGAR2_AIF_BCLK_DIR_MASK                  0x2000
#define LOCHNAGAR2_AIF_BCLK_DIR_SHIFT                     13
#define LOCHNAGAR2_AIF_SRC_MASK                       0x00FF
#define LOCHNAGAR2_AIF_SRC_SHIFT                           0

/* (0x001E - 0x0027)  CDC_MCLK1_CTRL - SOUNDCARD_MCLK_CTRL */
#define LOCHNAGAR2_CLK_ENA_MASK                       0x8000
#define LOCHNAGAR2_CLK_ENA_SHIFT                          15
#define LOCHNAGAR2_CLK_SRC_MASK                       0x00FF
#define LOCHNAGAR2_CLK_SRC_SHIFT                           0

/* (0x0031 - 0x009A)  GPIO_FPGA_GPIO1 - GPIO_DSP_GPIO20 */
#define LOCHNAGAR2_GPIO_SRC_MASK                      0x00FF
#define LOCHNAGAR2_GPIO_SRC_SHIFT                          0

/* (0x00B9 - 0x00C8)  GPIO_CHANNEL1 - GPIO_CHANNEL16 */
#define LOCHNAGAR2_GPIO_CHANNEL_STS_MASK              0x8000
#define LOCHNAGAR2_GPIO_CHANNEL_STS_SHIFT                 15
#define LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK              0x00FF
#define LOCHNAGAR2_GPIO_CHANNEL_SRC_SHIFT                  0

/* (0x00DF)  MINICARD_RESETS */
#define LOCHNAGAR2_DSP_RESET_MASK                     0x0002
#define LOCHNAGAR2_DSP_RESET_SHIFT                         1
#define LOCHNAGAR2_CDC_RESET_MASK                     0x0001
#define LOCHNAGAR2_CDC_RESET_SHIFT                         0

/* (0x00E3)  ANALOGUE_PATH_CTRL1 */
#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_MASK          0x8000
#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_SHIFT             15
#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_MASK      0x4000
#define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_SHIFT         14

/* (0x00E4)  ANALOGUE_PATH_CTRL2 */
#define LOCHNAGAR2_P2_INPUT_BIAS_ENA_MASK             0x0080
#define LOCHNAGAR2_P2_INPUT_BIAS_ENA_SHIFT                 7
#define LOCHNAGAR2_P1_INPUT_BIAS_ENA_MASK             0x0040
#define LOCHNAGAR2_P1_INPUT_BIAS_ENA_SHIFT                 6
#define LOCHNAGAR2_P2_MICBIAS_SRC_MASK                0x0038
#define LOCHNAGAR2_P2_MICBIAS_SRC_SHIFT                    3
#define LOCHNAGAR2_P1_MICBIAS_SRC_MASK                0x0007
#define LOCHNAGAR2_P1_MICBIAS_SRC_SHIFT                    0

/* (0x00F0)  COMMS_CTRL4 */
#define LOCHNAGAR2_CDC_CIF1MODE_MASK                  0x0001
#define LOCHNAGAR2_CDC_CIF1MODE_SHIFT                      0

/* (0x00FE)  SPDIF_CTRL */
#define LOCHNAGAR2_SPDIF_HWMODE_MASK                  0x0008
#define LOCHNAGAR2_SPDIF_HWMODE_SHIFT                      3
#define LOCHNAGAR2_SPDIF_RESET_MASK                   0x0001
#define LOCHNAGAR2_SPDIF_RESET_SHIFT                       0

/* (0x0108)  IMON_CTRL1 */
#define LOCHNAGAR2_IMON_ENA_MASK                      0x8000
#define LOCHNAGAR2_IMON_ENA_SHIFT                         15
#define LOCHNAGAR2_IMON_MEASURED_CHANNELS_MASK        0x03FC
#define LOCHNAGAR2_IMON_MEASURED_CHANNELS_SHIFT            2
#define LOCHNAGAR2_IMON_MODE_SEL_MASK                 0x0003
#define LOCHNAGAR2_IMON_MODE_SEL_SHIFT                     0

/* (0x0109)  IMON_CTRL2 */
#define LOCHNAGAR2_IMON_FSR_MASK                      0x03FF
#define LOCHNAGAR2_IMON_FSR_SHIFT                          0

/* (0x010A)  IMON_CTRL3 */
#define LOCHNAGAR2_IMON_DONE_MASK                     0x0004
#define LOCHNAGAR2_IMON_DONE_SHIFT                         2
#define LOCHNAGAR2_IMON_CONFIGURE_MASK                0x0002
#define LOCHNAGAR2_IMON_CONFIGURE_SHIFT                    1
#define LOCHNAGAR2_IMON_MEASURE_MASK                  0x0001
#define LOCHNAGAR2_IMON_MEASURE_SHIFT                      0

/* (0x010B)  IMON_CTRL4 */
#define LOCHNAGAR2_IMON_DATA_REQ_MASK                 0x0080
#define LOCHNAGAR2_IMON_DATA_REQ_SHIFT                     7
#define LOCHNAGAR2_IMON_CH_SEL_MASK                   0x0070
#define LOCHNAGAR2_IMON_CH_SEL_SHIFT                       4
#define LOCHNAGAR2_IMON_DATA_RDY_MASK                 0x0008
#define LOCHNAGAR2_IMON_DATA_RDY_SHIFT                     3
#define LOCHNAGAR2_IMON_CH_SRC_MASK                   0x0007
#define LOCHNAGAR2_IMON_CH_SRC_SHIFT                       0

/* (0x010C, 0x010D)  IMON_DATA1, IMON_DATA2 */
#define LOCHNAGAR2_IMON_DATA_MASK                     0xFFFF
#define LOCHNAGAR2_IMON_DATA_SHIFT                         0

/* (0x0116)  POWER_CTRL */
#define LOCHNAGAR2_PWR_ENA_MASK                       0x0001
#define LOCHNAGAR2_PWR_ENA_SHIFT                           0

/* (0x0119)  MICVDD_CTRL1 */
#define LOCHNAGAR2_MICVDD_REG_ENA_MASK                0x8000
#define LOCHNAGAR2_MICVDD_REG_ENA_SHIFT                   15

/* (0x011B)  MICVDD_CTRL2 */
#define LOCHNAGAR2_MICVDD_VSEL_MASK                   0x001F
#define LOCHNAGAR2_MICVDD_VSEL_SHIFT                       0

/* (0x011E)  VDDCORE_CDC_CTRL1 */
#define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_MASK           0x8000
#define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_SHIFT              15

/* (0x0120)  VDDCORE_CDC_CTRL2 */
#define LOCHNAGAR2_VDDCORE_CDC_VSEL_MASK              0x007F
#define LOCHNAGAR2_VDDCORE_CDC_VSEL_SHIFT                  0

#endif

Filemanager

Name Type Size Permission Actions
abx500 Folder 0755
arizona Folder 0755
atc260x Folder 0755
da9052 Folder 0755
da9055 Folder 0755
da9062 Folder 0755
da9063 Folder 0755
da9150 Folder 0755
madera Folder 0755
mt6323 Folder 0755
mt6328 Folder 0755
mt6331 Folder 0755
mt6332 Folder 0755
mt6357 Folder 0755
mt6358 Folder 0755
mt6359 Folder 0755
mt6359p Folder 0755
mt6397 Folder 0755
pcf50633 Folder 0755
samsung Folder 0755
syscon Folder 0755
wcd934x Folder 0755
wm831x Folder 0755
wm8350 Folder 0755
wm8994 Folder 0755
88pm80x.h File 9.85 KB 0644
88pm860x.h File 12.96 KB 0644
88pm886.h File 2.03 KB 0644
aat2870.h File 3.92 KB 0644
abx500.h File 2.34 KB 0644
ac100.h File 5.98 KB 0644
adp5520.h File 8.31 KB 0644
adp5585.h File 4.23 KB 0644
altera-a10sr.h File 2.89 KB 0644
altera-sysmgr.h File 725 B 0644
as3711.h File 2.74 KB 0644
as3722.h File 14.53 KB 0644
atmel-hlcdc.h File 2.37 KB 0644
axp20x.h File 25.08 KB 0644
bcm2835-pm.h File 262 B 0644
bcm590xx.h File 618 B 0644
bd9571mwv.h File 3.45 KB 0644
cgbc.h File 1.21 KB 0644
core.h File 4.2 KB 0644
cs40l50.h File 4.1 KB 0644
cs42l43-regs.h File 45.72 KB 0644
cs42l43.h File 2.21 KB 0644
da8xx-cfgchip.h File 6.88 KB 0644
da903x.h File 7.05 KB 0644
davinci_voicecodec.h File 2.6 KB 0644
db8500-prcmu.h File 21.33 KB 0644
dbx500-prcmu.h File 12.78 KB 0644
dln2.h File 3.53 KB 0644
ezx-pcap.h File 7.75 KB 0644
gsc.h File 1.78 KB 0644
hi6421-pmic.h File 1.16 KB 0644
hi655x-pmic.h File 1.91 KB 0644
idt82p33_reg.h File 3.01 KB 0644
idt8a340_reg.h File 30.34 KB 0644
idtRC38xxx_reg.h File 6.74 KB 0644
imx25-tsadc.h File 4.86 KB 0644
ingenic-tcu.h File 1.71 KB 0644
intel-m10-bmc.h File 9.87 KB 0644
intel_pmc_bxt.h File 1.51 KB 0644
intel_soc_pmic.h File 1.86 KB 0644
intel_soc_pmic_bxtwc.h File 1.6 KB 0644
intel_soc_pmic_mrfld.h File 2.23 KB 0644
ipaq-micro.h File 3.66 KB 0644
iqs62x.h File 2.9 KB 0644
janz.h File 846 B 0644
kempld.h File 4.03 KB 0644
khadas-mcu.h File 3.46 KB 0644
lm3533.h File 2.39 KB 0644
lochnagar.h File 1.59 KB 0644
lochnagar1_regs.h File 7.71 KB 0644
lochnagar2_regs.h File 15.19 KB 0644
lp3943.h File 2.54 KB 0644
lp873x.h File 8.29 KB 0644
lp87565.h File 7.41 KB 0644
lp8788-isink.h File 1.04 KB 0644
lp8788.h File 6.72 KB 0644
lpc_ich.h File 754 B 0644
max14577-private.h File 15.41 KB 0644
max14577.h File 2.23 KB 0644
max5970.h File 2.49 KB 0644
max77541.h File 2.77 KB 0644
max77620.h File 10.71 KB 0644
max77650.h File 1.84 KB 0644
max77686-private.h File 12.36 KB 0644
max77686.h File 1.99 KB 0644
max77693-common.h File 1.06 KB 0644
max77693-private.h File 17.31 KB 0644
max77693.h File 1.58 KB 0644
max77714.h File 1.7 KB 0644
max77843-private.h File 15.22 KB 0644
max8907.h File 7.38 KB 0644
max8925.h File 7.04 KB 0644
max8997-private.h File 11.77 KB 0644
max8997.h File 5.21 KB 0644
max8998-private.h File 4.35 KB 0644
max8998.h File 2.7 KB 0644
mc13783.h File 2.69 KB 0644
mc13892.h File 792 B 0644
mc13xxx.h File 7.59 KB 0644
mcp.h File 1.61 KB 0644
menelaus.h File 1.25 KB 0644
motorola-cpcap.h File 12.35 KB 0644
mp2629.h File 422 B 0644
mxs-lradc.h File 5.6 KB 0644
ntxec.h File 1009 B 0644
ocelot.h File 1.5 KB 0644
palmas.h File 148.58 KB 0644
qcom_rpm.h File 293 B 0644
qnap-mcu.h File 597 B 0644
rave-sp.h File 1.41 KB 0644
rc5t583.h File 9.28 KB 0644
rdc321x.h File 591 B 0644
retu.h File 723 B 0644
rk808.h File 37.91 KB 0644
rn5t618.h File 7.95 KB 0644
rohm-bd71815.h File 15.24 KB 0644
rohm-bd71828.h File 12.77 KB 0644
rohm-bd718x7.h File 8.83 KB 0644
rohm-bd957x.h File 4.26 KB 0644
rohm-bd96801.h File 5.71 KB 0644
rohm-generic.h File 2.66 KB 0644
rohm-shared.h File 631 B 0644
rsmu.h File 967 B 0644
rt5033-private.h File 8.64 KB 0644
rt5033.h File 598 B 0644
rz-mtu3.h File 6.6 KB 0644
sc27xx-pmic.h File 228 B 0644
si476x-core.h File 14.84 KB 0644
si476x-platform.h File 6.04 KB 0644
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sky81452.h File 354 B 0644
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stmfx.h File 3.93 KB 0644
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stpmic1.h File 5.58 KB 0644
stw481x.h File 1.39 KB 0644
sun4i-gpadc.h File 3.48 KB 0644
sy7636a.h File 1.04 KB 0644
syscon.h File 2 KB 0644
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ti-lmu-register.h File 5.53 KB 0644
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ti_am335x_tscadc.h File 5.74 KB 0644
tps6105x.h File 3.01 KB 0644
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