__  __    __   __  _____      _            _          _____ _          _ _ 
 |  \/  |   \ \ / / |  __ \    (_)          | |        / ____| |        | | |
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/***********************license start***************
 * Author: Cavium Networks
 *
 * Contact: [email protected]
 * This file is part of the OCTEON SDK
 *
 * Copyright (C) 2003-2018 Cavium, Inc.
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License, Version 2, as
 * published by the Free Software Foundation.
 *
 * This file is distributed in the hope that it will be useful, but
 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
 * NONINFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this file; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
 * or visit http://www.gnu.org/licenses/.
 *
 * This file may also be available under a different license from Cavium.
 * Contact Cavium Networks for more information
 ***********************license end**************************************/

#ifndef __CVMX_PCSXX_DEFS_H__
#define __CVMX_PCSXX_DEFS_H__

static inline uint64_t CVMX_PCSXX_10GBX_STATUS_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000828ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_BIST_STATUS_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000870ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_BIT_LOCK_STATUS_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000850ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_CONTROL1_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000800ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_CONTROL2_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000818ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_INT_EN_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000860ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_INT_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000858ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_LOG_ANL_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000868ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_MISC_CTL_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000848ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_RX_SYNC_STATES_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000838ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_SPD_ABIL_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000810ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_STATUS1_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000808ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_STATUS2_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000820ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_TX_RX_POLARITY_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000840ull) + (block_id) * 0x1000000ull;
}

static inline uint64_t CVMX_PCSXX_TX_RX_STATES_REG(unsigned long block_id)
{
	switch (cvmx_get_octeon_family()) {
	case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
	case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x8000000ull;
	case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
		return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
	}
	return CVMX_ADD_IO_SEG(0x00011800B0000830ull) + (block_id) * 0x1000000ull;
}

void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index);

union cvmx_pcsxx_10gbx_status_reg {
	uint64_t u64;
	struct cvmx_pcsxx_10gbx_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_13_63:51;
		uint64_t alignd:1;
		uint64_t pattst:1;
		uint64_t reserved_4_10:7;
		uint64_t l3sync:1;
		uint64_t l2sync:1;
		uint64_t l1sync:1;
		uint64_t l0sync:1;
#else
		uint64_t l0sync:1;
		uint64_t l1sync:1;
		uint64_t l2sync:1;
		uint64_t l3sync:1;
		uint64_t reserved_4_10:7;
		uint64_t pattst:1;
		uint64_t alignd:1;
		uint64_t reserved_13_63:51;
#endif
	} s;
};

union cvmx_pcsxx_bist_status_reg {
	uint64_t u64;
	struct cvmx_pcsxx_bist_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_1_63:63;
		uint64_t bist_status:1;
#else
		uint64_t bist_status:1;
		uint64_t reserved_1_63:63;
#endif
	} s;
};

union cvmx_pcsxx_bit_lock_status_reg {
	uint64_t u64;
	struct cvmx_pcsxx_bit_lock_status_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_4_63:60;
		uint64_t bitlck3:1;
		uint64_t bitlck2:1;
		uint64_t bitlck1:1;
		uint64_t bitlck0:1;
#else
		uint64_t bitlck0:1;
		uint64_t bitlck1:1;
		uint64_t bitlck2:1;
		uint64_t bitlck3:1;
		uint64_t reserved_4_63:60;
#endif
	} s;
};

union cvmx_pcsxx_control1_reg {
	uint64_t u64;
	struct cvmx_pcsxx_control1_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t reset:1;
		uint64_t loopbck1:1;
		uint64_t spdsel1:1;
		uint64_t reserved_12_12:1;
		uint64_t lo_pwr:1;
		uint64_t reserved_7_10:4;
		uint64_t spdsel0:1;
		uint64_t spd:4;
		uint64_t reserved_0_1:2;
#else
		uint64_t reserved_0_1:2;
		uint64_t spd:4;
		uint64_t spdsel0:1;
		uint64_t reserved_7_10:4;
		uint64_t lo_pwr:1;
		uint64_t reserved_12_12:1;
		uint64_t spdsel1:1;
		uint64_t loopbck1:1;
		uint64_t reset:1;
		uint64_t reserved_16_63:48;
#endif
	} s;
};

union cvmx_pcsxx_control2_reg {
	uint64_t u64;
	struct cvmx_pcsxx_control2_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_2_63:62;
		uint64_t type:2;
#else
		uint64_t type:2;
		uint64_t reserved_2_63:62;
#endif
	} s;
};

union cvmx_pcsxx_int_en_reg {
	uint64_t u64;
	struct cvmx_pcsxx_int_en_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_7_63:57;
		uint64_t dbg_sync_en:1;
		uint64_t algnlos_en:1;
		uint64_t synlos_en:1;
		uint64_t bitlckls_en:1;
		uint64_t rxsynbad_en:1;
		uint64_t rxbad_en:1;
		uint64_t txflt_en:1;
#else
		uint64_t txflt_en:1;
		uint64_t rxbad_en:1;
		uint64_t rxsynbad_en:1;
		uint64_t bitlckls_en:1;
		uint64_t synlos_en:1;
		uint64_t algnlos_en:1;
		uint64_t dbg_sync_en:1;
		uint64_t reserved_7_63:57;
#endif
	} s;
	struct cvmx_pcsxx_int_en_reg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_6_63:58;
		uint64_t algnlos_en:1;
		uint64_t synlos_en:1;
		uint64_t bitlckls_en:1;
		uint64_t rxsynbad_en:1;
		uint64_t rxbad_en:1;
		uint64_t txflt_en:1;
#else
		uint64_t txflt_en:1;
		uint64_t rxbad_en:1;
		uint64_t rxsynbad_en:1;
		uint64_t bitlckls_en:1;
		uint64_t synlos_en:1;
		uint64_t algnlos_en:1;
		uint64_t reserved_6_63:58;
#endif
	} cn52xx;
};

union cvmx_pcsxx_int_reg {
	uint64_t u64;
	struct cvmx_pcsxx_int_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_7_63:57;
		uint64_t dbg_sync:1;
		uint64_t algnlos:1;
		uint64_t synlos:1;
		uint64_t bitlckls:1;
		uint64_t rxsynbad:1;
		uint64_t rxbad:1;
		uint64_t txflt:1;
#else
		uint64_t txflt:1;
		uint64_t rxbad:1;
		uint64_t rxsynbad:1;
		uint64_t bitlckls:1;
		uint64_t synlos:1;
		uint64_t algnlos:1;
		uint64_t dbg_sync:1;
		uint64_t reserved_7_63:57;
#endif
	} s;
	struct cvmx_pcsxx_int_reg_cn52xx {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_6_63:58;
		uint64_t algnlos:1;
		uint64_t synlos:1;
		uint64_t bitlckls:1;
		uint64_t rxsynbad:1;
		uint64_t rxbad:1;
		uint64_t txflt:1;
#else
		uint64_t txflt:1;
		uint64_t rxbad:1;
		uint64_t rxsynbad:1;
		uint64_t bitlckls:1;
		uint64_t synlos:1;
		uint64_t algnlos:1;
		uint64_t reserved_6_63:58;
#endif
	} cn52xx;
};

union cvmx_pcsxx_log_anl_reg {
	uint64_t u64;
	struct cvmx_pcsxx_log_anl_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_7_63:57;
		uint64_t enc_mode:1;
		uint64_t drop_ln:2;
		uint64_t lafifovfl:1;
		uint64_t la_en:1;
		uint64_t pkt_sz:2;
#else
		uint64_t pkt_sz:2;
		uint64_t la_en:1;
		uint64_t lafifovfl:1;
		uint64_t drop_ln:2;
		uint64_t enc_mode:1;
		uint64_t reserved_7_63:57;
#endif
	} s;
};

union cvmx_pcsxx_misc_ctl_reg {
	uint64_t u64;
	struct cvmx_pcsxx_misc_ctl_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_4_63:60;
		uint64_t tx_swap:1;
		uint64_t rx_swap:1;
		uint64_t xaui:1;
		uint64_t gmxeno:1;
#else
		uint64_t gmxeno:1;
		uint64_t xaui:1;
		uint64_t rx_swap:1;
		uint64_t tx_swap:1;
		uint64_t reserved_4_63:60;
#endif
	} s;
};

union cvmx_pcsxx_rx_sync_states_reg {
	uint64_t u64;
	struct cvmx_pcsxx_rx_sync_states_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t sync3st:4;
		uint64_t sync2st:4;
		uint64_t sync1st:4;
		uint64_t sync0st:4;
#else
		uint64_t sync0st:4;
		uint64_t sync1st:4;
		uint64_t sync2st:4;
		uint64_t sync3st:4;
		uint64_t reserved_16_63:48;
#endif
	} s;
};

union cvmx_pcsxx_spd_abil_reg {
	uint64_t u64;
	struct cvmx_pcsxx_spd_abil_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_2_63:62;
		uint64_t tenpasst:1;
		uint64_t tengb:1;
#else
		uint64_t tengb:1;
		uint64_t tenpasst:1;
		uint64_t reserved_2_63:62;
#endif
	} s;
};

union cvmx_pcsxx_status1_reg {
	uint64_t u64;
	struct cvmx_pcsxx_status1_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_8_63:56;
		uint64_t flt:1;
		uint64_t reserved_3_6:4;
		uint64_t rcv_lnk:1;
		uint64_t lpable:1;
		uint64_t reserved_0_0:1;
#else
		uint64_t reserved_0_0:1;
		uint64_t lpable:1;
		uint64_t rcv_lnk:1;
		uint64_t reserved_3_6:4;
		uint64_t flt:1;
		uint64_t reserved_8_63:56;
#endif
	} s;
};

union cvmx_pcsxx_status2_reg {
	uint64_t u64;
	struct cvmx_pcsxx_status2_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_16_63:48;
		uint64_t dev:2;
		uint64_t reserved_12_13:2;
		uint64_t xmtflt:1;
		uint64_t rcvflt:1;
		uint64_t reserved_3_9:7;
		uint64_t tengb_w:1;
		uint64_t tengb_x:1;
		uint64_t tengb_r:1;
#else
		uint64_t tengb_r:1;
		uint64_t tengb_x:1;
		uint64_t tengb_w:1;
		uint64_t reserved_3_9:7;
		uint64_t rcvflt:1;
		uint64_t xmtflt:1;
		uint64_t reserved_12_13:2;
		uint64_t dev:2;
		uint64_t reserved_16_63:48;
#endif
	} s;
};

union cvmx_pcsxx_tx_rx_polarity_reg {
	uint64_t u64;
	struct cvmx_pcsxx_tx_rx_polarity_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_10_63:54;
		uint64_t xor_rxplrt:4;
		uint64_t xor_txplrt:4;
		uint64_t rxplrt:1;
		uint64_t txplrt:1;
#else
		uint64_t txplrt:1;
		uint64_t rxplrt:1;
		uint64_t xor_txplrt:4;
		uint64_t xor_rxplrt:4;
		uint64_t reserved_10_63:54;
#endif
	} s;
	struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_2_63:62;
		uint64_t rxplrt:1;
		uint64_t txplrt:1;
#else
		uint64_t txplrt:1;
		uint64_t rxplrt:1;
		uint64_t reserved_2_63:62;
#endif
	} cn52xxp1;
};

union cvmx_pcsxx_tx_rx_states_reg {
	uint64_t u64;
	struct cvmx_pcsxx_tx_rx_states_reg_s {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_14_63:50;
		uint64_t term_err:1;
		uint64_t syn3bad:1;
		uint64_t syn2bad:1;
		uint64_t syn1bad:1;
		uint64_t syn0bad:1;
		uint64_t rxbad:1;
		uint64_t algn_st:3;
		uint64_t rx_st:2;
		uint64_t tx_st:3;
#else
		uint64_t tx_st:3;
		uint64_t rx_st:2;
		uint64_t algn_st:3;
		uint64_t rxbad:1;
		uint64_t syn0bad:1;
		uint64_t syn1bad:1;
		uint64_t syn2bad:1;
		uint64_t syn3bad:1;
		uint64_t term_err:1;
		uint64_t reserved_14_63:50;
#endif
	} s;
	struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 {
#ifdef __BIG_ENDIAN_BITFIELD
		uint64_t reserved_13_63:51;
		uint64_t syn3bad:1;
		uint64_t syn2bad:1;
		uint64_t syn1bad:1;
		uint64_t syn0bad:1;
		uint64_t rxbad:1;
		uint64_t algn_st:3;
		uint64_t rx_st:2;
		uint64_t tx_st:3;
#else
		uint64_t tx_st:3;
		uint64_t rx_st:2;
		uint64_t algn_st:3;
		uint64_t rxbad:1;
		uint64_t syn0bad:1;
		uint64_t syn1bad:1;
		uint64_t syn2bad:1;
		uint64_t syn3bad:1;
		uint64_t reserved_13_63:51;
#endif
	} cn52xxp1;
};

#endif

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DIR : / usr/ src/ linux-headers-6.14.0-37/ arch/ mips/ include/ asm/ octeon/
Name Type Size Permission Actions
cvmx-address.h File 9.15 KB 0644
cvmx-agl-defs.h File 40.5 KB 0644
cvmx-asm.h File 5.08 KB 0644
cvmx-asxx-defs.h File 13.51 KB 0644
cvmx-boot-vector.h File 1.57 KB 0644
cvmx-bootinfo.h File 13.76 KB 0644
cvmx-bootmem.h File 11.49 KB 0644
cvmx-ciu-defs.h File 5.74 KB 0644
cvmx-ciu2-defs.h File 2.96 KB 0644
cvmx-ciu3-defs.h File 10.71 KB 0644
cvmx-cmd-queue.h File 18.46 KB 0644
cvmx-config.h File 6.31 KB 0644
cvmx-coremask.h File 2.13 KB 0644
cvmx-dbg-defs.h File 2.58 KB 0644
cvmx-dpi-defs.h File 19.96 KB 0644
cvmx-fau.h File 18.21 KB 0644
cvmx-fpa-defs.h File 27.66 KB 0644
cvmx-fpa.h File 7.47 KB 0644
cvmx-gmxx-defs.h File 54.86 KB 0644
cvmx-gpio-defs.h File 8.88 KB 0644
cvmx-helper-board.h File 4.56 KB 0644
cvmx-helper-errata.h File 1.25 KB 0644
cvmx-helper-jtag.h File 1.49 KB 0644
cvmx-helper-loop.h File 1.93 KB 0644
cvmx-helper-npi.h File 1.91 KB 0644
cvmx-helper-rgmii.h File 2.89 KB 0644
cvmx-helper-sgmii.h File 2.75 KB 0644
cvmx-helper-spi.h File 2.72 KB 0644
cvmx-helper-util.h File 5.23 KB 0644
cvmx-helper-xaui.h File 2.74 KB 0644
cvmx-helper.h File 5.49 KB 0644
cvmx-iob-defs.h File 19.54 KB 0644
cvmx-ipd-defs.h File 32.83 KB 0644
cvmx-ipd.h File 10.49 KB 0644
cvmx-l2c-defs.h File 7.94 KB 0644
cvmx-l2c.h File 11.12 KB 0644
cvmx-l2d-defs.h File 1.9 KB 0644
cvmx-l2t-defs.h File 4.98 KB 0644
cvmx-led-defs.h File 4.94 KB 0644
cvmx-lmcx-defs.h File 68.41 KB 0644
cvmx-mio-defs.h File 95.43 KB 0644
cvmx-mixx-defs.h File 9.85 KB 0644
cvmx-npei-defs.h File 82.99 KB 0644
cvmx-npi-defs.h File 58.21 KB 0644
cvmx-packet.h File 2.07 KB 0644
cvmx-pci-defs.h File 42.26 KB 0644
cvmx-pciercx-defs.h File 11.23 KB 0644
cvmx-pcsx-defs.h File 25.92 KB 0644
cvmx-pcsxx-defs.h File 18.95 KB 0644
cvmx-pemx-defs.h File 14.96 KB 0644
cvmx-pescx-defs.h File 13.42 KB 0644
cvmx-pexp-defs.h File 16.64 KB 0644
cvmx-pip-defs.h File 60.9 KB 0644
cvmx-pip.h File 16.01 KB 0644
cvmx-pko-defs.h File 47.31 KB 0644
cvmx-pko.h File 19.11 KB 0644
cvmx-pow-defs.h File 22.04 KB 0644
cvmx-pow.h File 63.85 KB 0644
cvmx-rnm-defs.h File 3.99 KB 0644
cvmx-rst-defs.h File 6.33 KB 0644
cvmx-scratch.h File 3.78 KB 0644
cvmx-sli-defs.h File 3.96 KB 0644
cvmx-spi.h File 8.93 KB 0644
cvmx-spinlock.h File 6.24 KB 0644
cvmx-spxx-defs.h File 10.56 KB 0644
cvmx-sriox-defs.h File 37.21 KB 0644
cvmx-srxx-defs.h File 3.65 KB 0644
cvmx-stxx-defs.h File 8.05 KB 0644
cvmx-sysinfo.h File 3.95 KB 0644
cvmx-uctlx-defs.h File 9.27 KB 0644
cvmx-wqe.h File 17.08 KB 0644
cvmx.h File 13.85 KB 0644
octeon-feature.h File 6.38 KB 0644
octeon-model.h File 16.49 KB 0644
octeon.h File 12.11 KB 0644
pci-octeon.h File 1.68 KB 0644

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