__  __    __   __  _____      _            _          _____ _          _ _ 
 |  \/  |   \ \ / / |  __ \    (_)          | |        / ____| |        | | |
 | \  / |_ __\ V /  | |__) | __ ___   ____ _| |_ ___  | (___ | |__   ___| | |
 | |\/| | '__|> <   |  ___/ '__| \ \ / / _` | __/ _ \  \___ \| '_ \ / _ \ | |
 | |  | | |_ / . \  | |   | |  | |\ V / (_| | ||  __/  ____) | | | |  __/ | |
 |_|  |_|_(_)_/ \_\ |_|   |_|  |_| \_/ \__,_|\__\___| |_____/|_| |_|\___V 2.1
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/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Chained IRQ handlers support.
 *
 * Copyright (C) 2011 ARM Ltd.
 */
#ifndef __IRQCHIP_CHAINED_IRQ_H
#define __IRQCHIP_CHAINED_IRQ_H

#include <linux/irq.h>

/*
 * Entry/exit functions for chained handlers where the primary IRQ chip
 * may implement either fasteoi or level-trigger flow control.
 */
static inline void chained_irq_enter(struct irq_chip *chip,
				     struct irq_desc *desc)
{
	/* FastEOI controllers require no action on entry. */
	if (chip->irq_eoi)
		return;

	if (chip->irq_mask_ack) {
		chip->irq_mask_ack(&desc->irq_data);
	} else {
		chip->irq_mask(&desc->irq_data);
		if (chip->irq_ack)
			chip->irq_ack(&desc->irq_data);
	}
}

static inline void chained_irq_exit(struct irq_chip *chip,
				    struct irq_desc *desc)
{
	if (chip->irq_eoi)
		chip->irq_eoi(&desc->irq_data);
	else
		chip->irq_unmask(&desc->irq_data);
}

#endif /* __IRQCHIP_CHAINED_IRQ_H */

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Name Type Size Permission Actions
arm-gic-common.h File 480 B 0644
arm-gic-v3-prio.h File 1.76 KB 0644
arm-gic-v3.h File 23.93 KB 0644
arm-gic-v4.h File 3.8 KB 0644
arm-gic.h File 5.26 KB 0644
arm-vgic-info.h File 1001 B 0644
arm-vic.h File 353 B 0644
chained_irq.h File 931 B 0644
irq-bcm2836.h File 1.89 KB 0644
irq-davinci-aintc.h File 674 B 0644
irq-davinci-cp-intc.h File 616 B 0644
irq-madera.h File 3.66 KB 0644
irq-omap-intc.h File 567 B 0644
irq-partition-percpu.h File 1.33 KB 0644
irq-sa11x0.h File 356 B 0644
riscv-aplic.h File 4.52 KB 0644
riscv-imsic.h File 2.32 KB 0644
xtensa-mx.h File 467 B 0644
xtensa-pic.h File 532 B 0644
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