__  __    __   __  _____      _            _          _____ _          _ _ 
 |  \/  |   \ \ / / |  __ \    (_)          | |        / ____| |        | | |
 | \  / |_ __\ V /  | |__) | __ ___   ____ _| |_ ___  | (___ | |__   ___| | |
 | |\/| | '__|> <   |  ___/ '__| \ \ / / _` | __/ _ \  \___ \| '_ \ / _ \ | |
 | |  | | |_ / . \  | |   | |  | |\ V / (_| | ||  __/  ____) | | | |  __/ | |
 |_|  |_|_(_)_/ \_\ |_|   |_|  |_| \_/ \__,_|\__\___| |_____/|_| |_|\___V 2.1
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# SPDX-License-Identifier: GPL-2.0
#
# Intel x86 Platform-Specific Drivers
#

config INTEL_PMC_CORE
	tristate "Intel PMC Core driver"
	depends on PCI
	depends on ACPI
	depends on INTEL_PMT_TELEMETRY
	help
	  The Intel Platform Controller Hub for Intel Core SoCs provides access
	  to Power Management Controller registers via various interfaces. This
	  driver can utilize debugging capabilities and supported features as
	  exposed by the Power Management Controller. It also may perform some
	  tasks in the PMC in order to enable transition into the SLPS0 state.
	  It should be selected on all Intel platforms supported by the driver.

	  Supported features:
		- SLP_S0_RESIDENCY counter
		- PCH IP Power Gating status
		- LTR Ignore / LTR Show
		- MPHY/PLL gating status (Sunrisepoint PCH only)
		- SLPS0 Debug registers (Cannonlake/Icelake PCH)
		- Low Power Mode registers (Tigerlake and beyond)
		- PMC quirks as needed to enable SLPS0/S0ix

Filemanager

Name Type Size Permission Actions
Kconfig File 949 B 0644
Makefile File 323 B 0644
Filemanager