__  __    __   __  _____      _            _          _____ _          _ _ 
 |  \/  |   \ \ / / |  __ \    (_)          | |        / ____| |        | | |
 | \  / |_ __\ V /  | |__) | __ ___   ____ _| |_ ___  | (___ | |__   ___| | |
 | |\/| | '__|> <   |  ___/ '__| \ \ / / _` | __/ _ \  \___ \| '_ \ / _ \ | |
 | |  | | |_ / . \  | |   | |  | |\ V / (_| | ||  __/  ____) | | | |  __/ | |
 |_|  |_|_(_)_/ \_\ |_|   |_|  |_| \_/ \__,_|\__\___| |_____/|_| |_|\___V 2.1
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# SPDX-License-Identifier: GPL-2.0
config CLK_INTEL_SOCFPGA
	bool "Intel SoCFPGA family clock support" if COMPILE_TEST && !ARCH_INTEL_SOCFPGA
	default ARCH_INTEL_SOCFPGA
	help
	  Support for the clock controllers present on Intel SoCFPGA and eASIC
	  devices like Aria, Cyclone, Stratix 10, Agilex and N5X eASIC.

if CLK_INTEL_SOCFPGA

config CLK_INTEL_SOCFPGA32
	bool "Intel Aria / Cyclone clock controller support" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
	default ARM && ARCH_INTEL_SOCFPGA

config CLK_INTEL_SOCFPGA64
	bool "Intel Stratix / Agilex / N5X clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA)
	default ARM64 && ARCH_INTEL_SOCFPGA

endif # CLK_INTEL_SOCFPGA

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