__  __    __   __  _____      _            _          _____ _          _ _ 
 |  \/  |   \ \ / / |  __ \    (_)          | |        / ____| |        | | |
 | \  / |_ __\ V /  | |__) | __ ___   ____ _| |_ ___  | (___ | |__   ___| | |
 | |\/| | '__|> <   |  ___/ '__| \ \ / / _` | __/ _ \  \___ \| '_ \ / _ \ | |
 | |  | | |_ / . \  | |   | |  | |\ V / (_| | ||  __/  ____) | | | |  __/ | |
 |_|  |_|_(_)_/ \_\ |_|   |_|  |_| \_/ \__,_|\__\___| |_____/|_| |_|\___V 2.1
 if you need WebShell for Seo everyday contact me on Telegram
 Telegram Address : @jackleet
        
        
For_More_Tools: Telegram: @jackleet | Bulk Smtp support mail sender | Business Mail Collector | Mail Bouncer All Mail | Bulk Office Mail Validator | Html Letter private



Upload:

Command:

[email protected]: ~ $
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2006-2008 PA Semi, Inc
 *
 * Hardware register layout and descriptor formats for the on-board
 * DMA engine on PA Semi PWRficient. Used by ethernet, function and security
 * drivers.
 */

#ifndef ASM_PASEMI_DMA_H
#define ASM_PASEMI_DMA_H

/* status register layout in IOB region, at 0xfb800000 */
struct pasdma_status {
	u64 rx_sta[64];		/* RX channel status */
	u64 tx_sta[20];		/* TX channel status */
};


/* All these registers live in the PCI configuration space for the DMA PCI
 * device. Use the normal PCI config access functions for them.
 */
enum {
	PAS_DMA_CAP_TXCH  = 0x44,	/* Transmit Channel Info      */
	PAS_DMA_CAP_RXCH  = 0x48,	/* Transmit Channel Info      */
	PAS_DMA_CAP_IFI	  = 0x4c,	/* Interface Info	      */
	PAS_DMA_COM_TXCMD = 0x100,	/* Transmit Command Register  */
	PAS_DMA_COM_TXSTA = 0x104,	/* Transmit Status Register   */
	PAS_DMA_COM_RXCMD = 0x108,	/* Receive Command Register   */
	PAS_DMA_COM_RXSTA = 0x10c,	/* Receive Status Register    */
	PAS_DMA_COM_CFG   = 0x114,	/* Common config reg	      */
	PAS_DMA_TXF_SFLG0 = 0x140,	/* Set flags                  */
	PAS_DMA_TXF_SFLG1 = 0x144,	/* Set flags                  */
	PAS_DMA_TXF_CFLG0 = 0x148,	/* Set flags                  */
	PAS_DMA_TXF_CFLG1 = 0x14c,	/* Set flags                  */
};


#define PAS_DMA_CAP_TXCH_TCHN_M	0x00ff0000 /* # of TX channels */
#define PAS_DMA_CAP_TXCH_TCHN_S	16

#define PAS_DMA_CAP_RXCH_RCHN_M	0x00ff0000 /* # of RX channels */
#define PAS_DMA_CAP_RXCH_RCHN_S	16

#define PAS_DMA_CAP_IFI_IOFF_M	0xff000000 /* Cfg reg for intf pointers */
#define PAS_DMA_CAP_IFI_IOFF_S	24
#define PAS_DMA_CAP_IFI_NIN_M	0x00ff0000 /* # of interfaces */
#define PAS_DMA_CAP_IFI_NIN_S	16

#define PAS_DMA_COM_TXCMD_EN	0x00000001 /* enable */
#define PAS_DMA_COM_TXSTA_ACT	0x00000001 /* active */
#define PAS_DMA_COM_RXCMD_EN	0x00000001 /* enable */
#define PAS_DMA_COM_RXSTA_ACT	0x00000001 /* active */


/* Per-interface and per-channel registers */
#define _PAS_DMA_RXINT_STRIDE		0x20
#define PAS_DMA_RXINT_RCMDSTA(i)	(0x200+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_RCMDSTA_EN	0x00000001
#define    PAS_DMA_RXINT_RCMDSTA_ST	0x00000002
#define    PAS_DMA_RXINT_RCMDSTA_MBT	0x00000008
#define    PAS_DMA_RXINT_RCMDSTA_MDR	0x00000010
#define    PAS_DMA_RXINT_RCMDSTA_MOO	0x00000020
#define    PAS_DMA_RXINT_RCMDSTA_MBP	0x00000040
#define    PAS_DMA_RXINT_RCMDSTA_BT	0x00000800
#define    PAS_DMA_RXINT_RCMDSTA_DR	0x00001000
#define    PAS_DMA_RXINT_RCMDSTA_OO	0x00002000
#define    PAS_DMA_RXINT_RCMDSTA_BP	0x00004000
#define    PAS_DMA_RXINT_RCMDSTA_TB	0x00008000
#define    PAS_DMA_RXINT_RCMDSTA_ACT	0x00010000
#define    PAS_DMA_RXINT_RCMDSTA_DROPS_M	0xfffe0000
#define    PAS_DMA_RXINT_RCMDSTA_DROPS_S	17
#define PAS_DMA_RXINT_CFG(i)		(0x204+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_CFG_RBP	0x80000000
#define    PAS_DMA_RXINT_CFG_ITRR	0x40000000
#define    PAS_DMA_RXINT_CFG_DHL_M	0x07000000
#define    PAS_DMA_RXINT_CFG_DHL_S	24
#define    PAS_DMA_RXINT_CFG_DHL(x)	(((x) << PAS_DMA_RXINT_CFG_DHL_S) & \
					 PAS_DMA_RXINT_CFG_DHL_M)
#define    PAS_DMA_RXINT_CFG_ITR	0x00400000
#define    PAS_DMA_RXINT_CFG_LW		0x00200000
#define    PAS_DMA_RXINT_CFG_L2		0x00100000
#define    PAS_DMA_RXINT_CFG_HEN	0x00080000
#define    PAS_DMA_RXINT_CFG_WIF	0x00000002
#define    PAS_DMA_RXINT_CFG_WIL	0x00000001

#define PAS_DMA_RXINT_INCR(i)		(0x210+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_INCR_INCR_M	0x0000ffff
#define    PAS_DMA_RXINT_INCR_INCR_S	0
#define    PAS_DMA_RXINT_INCR_INCR(x)	((x) & 0x0000ffff)
#define PAS_DMA_RXINT_BASEL(i)		(0x218+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_BASEL_BRBL(x)	((x) & ~0x3f)
#define PAS_DMA_RXINT_BASEU(i)		(0x21c+(i)*_PAS_DMA_RXINT_STRIDE)
#define    PAS_DMA_RXINT_BASEU_BRBH(x)	((x) & 0xfff)
#define    PAS_DMA_RXINT_BASEU_SIZ_M	0x3fff0000	/* # of cache lines worth of buffer ring */
#define    PAS_DMA_RXINT_BASEU_SIZ_S	16		/* 0 = 16K */
#define    PAS_DMA_RXINT_BASEU_SIZ(x)	(((x) << PAS_DMA_RXINT_BASEU_SIZ_S) & \
					 PAS_DMA_RXINT_BASEU_SIZ_M)


#define _PAS_DMA_TXCHAN_STRIDE	0x20    /* Size per channel		*/
#define _PAS_DMA_TXCHAN_TCMDSTA	0x300	/* Command / Status		*/
#define _PAS_DMA_TXCHAN_CFG	0x304	/* Configuration		*/
#define _PAS_DMA_TXCHAN_DSCRBU	0x308	/* Descriptor BU Allocation	*/
#define _PAS_DMA_TXCHAN_INCR	0x310	/* Descriptor increment		*/
#define _PAS_DMA_TXCHAN_CNT	0x314	/* Descriptor count/offset	*/
#define _PAS_DMA_TXCHAN_BASEL	0x318	/* Descriptor ring base (low)	*/
#define _PAS_DMA_TXCHAN_BASEU	0x31c	/*			(high)	*/
#define PAS_DMA_TXCHAN_TCMDSTA(c) (0x300+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define    PAS_DMA_TXCHAN_TCMDSTA_EN	0x00000001	/* Enabled */
#define    PAS_DMA_TXCHAN_TCMDSTA_ST	0x00000002	/* Stop interface */
#define    PAS_DMA_TXCHAN_TCMDSTA_ACT	0x00010000	/* Active */
#define    PAS_DMA_TXCHAN_TCMDSTA_SZ	0x00000800
#define    PAS_DMA_TXCHAN_TCMDSTA_DB	0x00000400
#define    PAS_DMA_TXCHAN_TCMDSTA_DE	0x00000200
#define    PAS_DMA_TXCHAN_TCMDSTA_DA	0x00000100
#define PAS_DMA_TXCHAN_CFG(c)     (0x304+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define    PAS_DMA_TXCHAN_CFG_TY_IFACE	0x00000000	/* Type = interface */
#define    PAS_DMA_TXCHAN_CFG_TY_COPY	0x00000001	/* Type = copy only */
#define    PAS_DMA_TXCHAN_CFG_TY_FUNC	0x00000002	/* Type = function */
#define    PAS_DMA_TXCHAN_CFG_TY_XOR	0x00000003	/* Type = xor only */
#define    PAS_DMA_TXCHAN_CFG_TATTR_M	0x0000003c
#define    PAS_DMA_TXCHAN_CFG_TATTR_S	2
#define    PAS_DMA_TXCHAN_CFG_TATTR(x)	(((x) << PAS_DMA_TXCHAN_CFG_TATTR_S) & \
					 PAS_DMA_TXCHAN_CFG_TATTR_M)
#define    PAS_DMA_TXCHAN_CFG_LPDQ	0x00000800
#define    PAS_DMA_TXCHAN_CFG_LPSQ	0x00000400
#define    PAS_DMA_TXCHAN_CFG_WT_M	0x000003c0
#define    PAS_DMA_TXCHAN_CFG_WT_S	6
#define    PAS_DMA_TXCHAN_CFG_WT(x)	(((x) << PAS_DMA_TXCHAN_CFG_WT_S) & \
					 PAS_DMA_TXCHAN_CFG_WT_M)
#define    PAS_DMA_TXCHAN_CFG_TRD	0x00010000	/* translate data */
#define    PAS_DMA_TXCHAN_CFG_TRR	0x00008000	/* translate rings */
#define    PAS_DMA_TXCHAN_CFG_UP	0x00004000	/* update tx descr when sent */
#define    PAS_DMA_TXCHAN_CFG_CL	0x00002000	/* Clean last line */
#define    PAS_DMA_TXCHAN_CFG_CF	0x00001000	/* Clean first line */
#define PAS_DMA_TXCHAN_INCR(c)    (0x310+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define PAS_DMA_TXCHAN_BASEL(c)   (0x318+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define    PAS_DMA_TXCHAN_BASEL_BRBL_M	0xffffffc0
#define    PAS_DMA_TXCHAN_BASEL_BRBL_S	0
#define    PAS_DMA_TXCHAN_BASEL_BRBL(x)	(((x) << PAS_DMA_TXCHAN_BASEL_BRBL_S) & \
					 PAS_DMA_TXCHAN_BASEL_BRBL_M)
#define PAS_DMA_TXCHAN_BASEU(c)   (0x31c+(c)*_PAS_DMA_TXCHAN_STRIDE)
#define    PAS_DMA_TXCHAN_BASEU_BRBH_M	0x00000fff
#define    PAS_DMA_TXCHAN_BASEU_BRBH_S	0
#define    PAS_DMA_TXCHAN_BASEU_BRBH(x)	(((x) << PAS_DMA_TXCHAN_BASEU_BRBH_S) & \
					 PAS_DMA_TXCHAN_BASEU_BRBH_M)
/* # of cache lines worth of buffer ring */
#define    PAS_DMA_TXCHAN_BASEU_SIZ_M	0x3fff0000
#define    PAS_DMA_TXCHAN_BASEU_SIZ_S	16		/* 0 = 16K */
#define    PAS_DMA_TXCHAN_BASEU_SIZ(x)	(((x) << PAS_DMA_TXCHAN_BASEU_SIZ_S) & \
					 PAS_DMA_TXCHAN_BASEU_SIZ_M)

#define _PAS_DMA_RXCHAN_STRIDE	0x20    /* Size per channel		*/
#define _PAS_DMA_RXCHAN_CCMDSTA	0x800	/* Command / Status		*/
#define _PAS_DMA_RXCHAN_CFG	0x804	/* Configuration		*/
#define _PAS_DMA_RXCHAN_INCR	0x810	/* Descriptor increment		*/
#define _PAS_DMA_RXCHAN_CNT	0x814	/* Descriptor count/offset	*/
#define _PAS_DMA_RXCHAN_BASEL	0x818	/* Descriptor ring base (low)	*/
#define _PAS_DMA_RXCHAN_BASEU	0x81c	/*			(high)	*/
#define PAS_DMA_RXCHAN_CCMDSTA(c) (0x800+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define    PAS_DMA_RXCHAN_CCMDSTA_EN	0x00000001	/* Enabled */
#define    PAS_DMA_RXCHAN_CCMDSTA_ST	0x00000002	/* Stop interface */
#define    PAS_DMA_RXCHAN_CCMDSTA_ACT	0x00010000	/* Active */
#define    PAS_DMA_RXCHAN_CCMDSTA_DU	0x00020000
#define    PAS_DMA_RXCHAN_CCMDSTA_OD	0x00002000
#define    PAS_DMA_RXCHAN_CCMDSTA_FD	0x00001000
#define    PAS_DMA_RXCHAN_CCMDSTA_DT	0x00000800
#define PAS_DMA_RXCHAN_CFG(c)     (0x804+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define    PAS_DMA_RXCHAN_CFG_CTR	0x00000400
#define    PAS_DMA_RXCHAN_CFG_HBU_M	0x00000380
#define    PAS_DMA_RXCHAN_CFG_HBU_S	7
#define    PAS_DMA_RXCHAN_CFG_HBU(x)	(((x) << PAS_DMA_RXCHAN_CFG_HBU_S) & \
					 PAS_DMA_RXCHAN_CFG_HBU_M)
#define PAS_DMA_RXCHAN_INCR(c)    (0x810+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define PAS_DMA_RXCHAN_BASEL(c)   (0x818+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define    PAS_DMA_RXCHAN_BASEL_BRBL_M	0xffffffc0
#define    PAS_DMA_RXCHAN_BASEL_BRBL_S	0
#define    PAS_DMA_RXCHAN_BASEL_BRBL(x)	(((x) << PAS_DMA_RXCHAN_BASEL_BRBL_S) & \
					 PAS_DMA_RXCHAN_BASEL_BRBL_M)
#define PAS_DMA_RXCHAN_BASEU(c)   (0x81c+(c)*_PAS_DMA_RXCHAN_STRIDE)
#define    PAS_DMA_RXCHAN_BASEU_BRBH_M	0x00000fff
#define    PAS_DMA_RXCHAN_BASEU_BRBH_S	0
#define    PAS_DMA_RXCHAN_BASEU_BRBH(x)	(((x) << PAS_DMA_RXCHAN_BASEU_BRBH_S) & \
					 PAS_DMA_RXCHAN_BASEU_BRBH_M)
/* # of cache lines worth of buffer ring */
#define    PAS_DMA_RXCHAN_BASEU_SIZ_M	0x3fff0000
#define    PAS_DMA_RXCHAN_BASEU_SIZ_S	16		/* 0 = 16K */
#define    PAS_DMA_RXCHAN_BASEU_SIZ(x)	(((x) << PAS_DMA_RXCHAN_BASEU_SIZ_S) & \
					 PAS_DMA_RXCHAN_BASEU_SIZ_M)

#define    PAS_STATUS_PCNT_M		0x000000000000ffffull
#define    PAS_STATUS_PCNT_S		0
#define    PAS_STATUS_DCNT_M		0x00000000ffff0000ull
#define    PAS_STATUS_DCNT_S		16
#define    PAS_STATUS_BPCNT_M		0x0000ffff00000000ull
#define    PAS_STATUS_BPCNT_S		32
#define    PAS_STATUS_CAUSE_M		0xf000000000000000ull
#define    PAS_STATUS_TIMER		0x1000000000000000ull
#define    PAS_STATUS_ERROR		0x2000000000000000ull
#define    PAS_STATUS_SOFT		0x4000000000000000ull
#define    PAS_STATUS_INT		0x8000000000000000ull

#define PAS_IOB_COM_PKTHDRCNT		0x120
#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR1_M	0x0fff0000
#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR1_S	16
#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR0_M	0x00000fff
#define    PAS_IOB_COM_PKTHDRCNT_PKTHDR0_S	0

#define PAS_IOB_DMA_RXCH_CFG(i)		(0x1100 + (i)*4)
#define    PAS_IOB_DMA_RXCH_CFG_CNTTH_M		0x00000fff
#define    PAS_IOB_DMA_RXCH_CFG_CNTTH_S		0
#define    PAS_IOB_DMA_RXCH_CFG_CNTTH(x)	(((x) << PAS_IOB_DMA_RXCH_CFG_CNTTH_S) & \
						 PAS_IOB_DMA_RXCH_CFG_CNTTH_M)
#define PAS_IOB_DMA_TXCH_CFG(i)		(0x1200 + (i)*4)
#define    PAS_IOB_DMA_TXCH_CFG_CNTTH_M		0x00000fff
#define    PAS_IOB_DMA_TXCH_CFG_CNTTH_S		0
#define    PAS_IOB_DMA_TXCH_CFG_CNTTH(x)	(((x) << PAS_IOB_DMA_TXCH_CFG_CNTTH_S) & \
						 PAS_IOB_DMA_TXCH_CFG_CNTTH_M)
#define PAS_IOB_DMA_RXCH_STAT(i)	(0x1300 + (i)*4)
#define    PAS_IOB_DMA_RXCH_STAT_INTGEN	0x00001000
#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_M	0x00000fff
#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL_S	0
#define    PAS_IOB_DMA_RXCH_STAT_CNTDEL(x)	(((x) << PAS_IOB_DMA_RXCH_STAT_CNTDEL_S) &\
						 PAS_IOB_DMA_RXCH_STAT_CNTDEL_M)
#define PAS_IOB_DMA_TXCH_STAT(i)	(0x1400 + (i)*4)
#define    PAS_IOB_DMA_TXCH_STAT_INTGEN	0x00001000
#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_M	0x00000fff
#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL_S	0
#define    PAS_IOB_DMA_TXCH_STAT_CNTDEL(x)	(((x) << PAS_IOB_DMA_TXCH_STAT_CNTDEL_S) &\
						 PAS_IOB_DMA_TXCH_STAT_CNTDEL_M)
#define PAS_IOB_DMA_RXCH_RESET(i)	(0x1500 + (i)*4)
#define    PAS_IOB_DMA_RXCH_RESET_PCNT_M	0xffff0000
#define    PAS_IOB_DMA_RXCH_RESET_PCNT_S	16
#define    PAS_IOB_DMA_RXCH_RESET_PCNT(x)	(((x) << PAS_IOB_DMA_RXCH_RESET_PCNT_S) & \
						 PAS_IOB_DMA_RXCH_RESET_PCNT_M)
#define    PAS_IOB_DMA_RXCH_RESET_PCNTRST	0x00000020
#define    PAS_IOB_DMA_RXCH_RESET_DCNTRST	0x00000010
#define    PAS_IOB_DMA_RXCH_RESET_TINTC		0x00000008
#define    PAS_IOB_DMA_RXCH_RESET_DINTC		0x00000004
#define    PAS_IOB_DMA_RXCH_RESET_SINTC		0x00000002
#define    PAS_IOB_DMA_RXCH_RESET_PINTC		0x00000001
#define PAS_IOB_DMA_TXCH_RESET(i)	(0x1600 + (i)*4)
#define    PAS_IOB_DMA_TXCH_RESET_PCNT_M	0xffff0000
#define    PAS_IOB_DMA_TXCH_RESET_PCNT_S	16
#define    PAS_IOB_DMA_TXCH_RESET_PCNT(x)	(((x) << PAS_IOB_DMA_TXCH_RESET_PCNT_S) & \
						 PAS_IOB_DMA_TXCH_RESET_PCNT_M)
#define    PAS_IOB_DMA_TXCH_RESET_PCNTRST	0x00000020
#define    PAS_IOB_DMA_TXCH_RESET_DCNTRST	0x00000010
#define    PAS_IOB_DMA_TXCH_RESET_TINTC		0x00000008
#define    PAS_IOB_DMA_TXCH_RESET_DINTC		0x00000004
#define    PAS_IOB_DMA_TXCH_RESET_SINTC		0x00000002
#define    PAS_IOB_DMA_TXCH_RESET_PINTC		0x00000001

#define PAS_IOB_DMA_COM_TIMEOUTCFG		0x1700
#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M	0x00ffffff
#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S	0
#define    PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(x)	(((x) << PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_S) & \
						 PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT_M)

/* Transmit descriptor fields */
#define	XCT_MACTX_T		0x8000000000000000ull
#define	XCT_MACTX_ST		0x4000000000000000ull
#define XCT_MACTX_NORES		0x0000000000000000ull
#define XCT_MACTX_8BRES		0x1000000000000000ull
#define XCT_MACTX_24BRES	0x2000000000000000ull
#define XCT_MACTX_40BRES	0x3000000000000000ull
#define XCT_MACTX_I		0x0800000000000000ull
#define XCT_MACTX_O		0x0400000000000000ull
#define XCT_MACTX_E		0x0200000000000000ull
#define XCT_MACTX_VLAN_M	0x0180000000000000ull
#define XCT_MACTX_VLAN_NOP	0x0000000000000000ull
#define XCT_MACTX_VLAN_REMOVE	0x0080000000000000ull
#define XCT_MACTX_VLAN_INSERT   0x0100000000000000ull
#define XCT_MACTX_VLAN_REPLACE  0x0180000000000000ull
#define XCT_MACTX_CRC_M		0x0060000000000000ull
#define XCT_MACTX_CRC_NOP	0x0000000000000000ull
#define XCT_MACTX_CRC_INSERT	0x0020000000000000ull
#define XCT_MACTX_CRC_PAD	0x0040000000000000ull
#define XCT_MACTX_CRC_REPLACE	0x0060000000000000ull
#define XCT_MACTX_SS		0x0010000000000000ull
#define XCT_MACTX_LLEN_M	0x00007fff00000000ull
#define XCT_MACTX_LLEN_S	32ull
#define XCT_MACTX_LLEN(x)	((((long)(x)) << XCT_MACTX_LLEN_S) & \
				 XCT_MACTX_LLEN_M)
#define XCT_MACTX_IPH_M		0x00000000f8000000ull
#define XCT_MACTX_IPH_S		27ull
#define XCT_MACTX_IPH(x)	((((long)(x)) << XCT_MACTX_IPH_S) & \
				 XCT_MACTX_IPH_M)
#define XCT_MACTX_IPO_M		0x0000000007c00000ull
#define XCT_MACTX_IPO_S		22ull
#define XCT_MACTX_IPO(x)	((((long)(x)) << XCT_MACTX_IPO_S) & \
				 XCT_MACTX_IPO_M)
#define XCT_MACTX_CSUM_M	0x0000000000000060ull
#define XCT_MACTX_CSUM_NOP	0x0000000000000000ull
#define XCT_MACTX_CSUM_TCP	0x0000000000000040ull
#define XCT_MACTX_CSUM_UDP	0x0000000000000060ull
#define XCT_MACTX_V6		0x0000000000000010ull
#define XCT_MACTX_C		0x0000000000000004ull
#define XCT_MACTX_AL2		0x0000000000000002ull

/* Receive descriptor fields */
#define	XCT_MACRX_T		0x8000000000000000ull
#define	XCT_MACRX_ST		0x4000000000000000ull
#define XCT_MACRX_RR_M		0x3000000000000000ull
#define XCT_MACRX_RR_NORES	0x0000000000000000ull
#define XCT_MACRX_RR_8BRES	0x1000000000000000ull
#define XCT_MACRX_O		0x0400000000000000ull
#define XCT_MACRX_E		0x0200000000000000ull
#define XCT_MACRX_FF		0x0100000000000000ull
#define XCT_MACRX_PF		0x0080000000000000ull
#define XCT_MACRX_OB		0x0040000000000000ull
#define XCT_MACRX_OD		0x0020000000000000ull
#define XCT_MACRX_FS		0x0010000000000000ull
#define XCT_MACRX_NB_M		0x000fc00000000000ull
#define XCT_MACRX_NB_S		46ULL
#define XCT_MACRX_NB(x)		((((long)(x)) << XCT_MACRX_NB_S) & \
				 XCT_MACRX_NB_M)
#define XCT_MACRX_LLEN_M	0x00003fff00000000ull
#define XCT_MACRX_LLEN_S	32ULL
#define XCT_MACRX_LLEN(x)	((((long)(x)) << XCT_MACRX_LLEN_S) & \
				 XCT_MACRX_LLEN_M)
#define XCT_MACRX_CRC		0x0000000080000000ull
#define XCT_MACRX_LEN_M		0x0000000060000000ull
#define XCT_MACRX_LEN_TOOSHORT	0x0000000020000000ull
#define XCT_MACRX_LEN_BELOWMIN	0x0000000040000000ull
#define XCT_MACRX_LEN_TRUNC	0x0000000060000000ull
#define XCT_MACRX_CAST_M	0x0000000018000000ull
#define XCT_MACRX_CAST_UNI	0x0000000000000000ull
#define XCT_MACRX_CAST_MULTI	0x0000000008000000ull
#define XCT_MACRX_CAST_BROAD	0x0000000010000000ull
#define XCT_MACRX_CAST_PAUSE	0x0000000018000000ull
#define XCT_MACRX_VLC_M		0x0000000006000000ull
#define XCT_MACRX_FM		0x0000000001000000ull
#define XCT_MACRX_HTY_M		0x0000000000c00000ull
#define XCT_MACRX_HTY_IPV4_OK	0x0000000000000000ull
#define XCT_MACRX_HTY_IPV6 	0x0000000000400000ull
#define XCT_MACRX_HTY_IPV4_BAD	0x0000000000800000ull
#define XCT_MACRX_HTY_NONIP	0x0000000000c00000ull
#define XCT_MACRX_IPP_M		0x00000000003f0000ull
#define XCT_MACRX_IPP_S		16
#define XCT_MACRX_CSUM_M	0x000000000000ffffull
#define XCT_MACRX_CSUM_S	0

#define XCT_PTR_T		0x8000000000000000ull
#define XCT_PTR_LEN_M		0x7ffff00000000000ull
#define XCT_PTR_LEN_S		44
#define XCT_PTR_LEN(x)		((((long)(x)) << XCT_PTR_LEN_S) & \
				 XCT_PTR_LEN_M)
#define XCT_PTR_ADDR_M		0x00000fffffffffffull
#define XCT_PTR_ADDR_S		0
#define XCT_PTR_ADDR(x)		((((long)(x)) << XCT_PTR_ADDR_S) & \
				 XCT_PTR_ADDR_M)

/* Receive interface 8byte result fields */
#define XCT_RXRES_8B_L4O_M	0xff00000000000000ull
#define XCT_RXRES_8B_L4O_S	56
#define XCT_RXRES_8B_RULE_M	0x00ffff0000000000ull
#define XCT_RXRES_8B_RULE_S	40
#define XCT_RXRES_8B_EVAL_M	0x000000ffff000000ull
#define XCT_RXRES_8B_EVAL_S	24
#define XCT_RXRES_8B_HTYPE_M	0x0000000000f00000ull
#define XCT_RXRES_8B_HASH_M	0x00000000000fffffull
#define XCT_RXRES_8B_HASH_S	0

/* Receive interface buffer fields */
#define XCT_RXB_LEN_M		0x0ffff00000000000ull
#define XCT_RXB_LEN_S		44
#define XCT_RXB_LEN(x)		((((long)(x)) << XCT_RXB_LEN_S) & \
				 XCT_RXB_LEN_M)
#define XCT_RXB_ADDR_M		0x00000fffffffffffull
#define XCT_RXB_ADDR_S		0
#define XCT_RXB_ADDR(x)		((((long)(x)) << XCT_RXB_ADDR_S) & \
				 XCT_RXB_ADDR_M)

/* Copy descriptor fields */
#define XCT_COPY_T		0x8000000000000000ull
#define XCT_COPY_ST		0x4000000000000000ull
#define XCT_COPY_RR_M		0x3000000000000000ull
#define XCT_COPY_RR_NORES	0x0000000000000000ull
#define XCT_COPY_RR_8BRES	0x1000000000000000ull
#define XCT_COPY_RR_24BRES	0x2000000000000000ull
#define XCT_COPY_RR_40BRES	0x3000000000000000ull
#define XCT_COPY_I		0x0800000000000000ull
#define XCT_COPY_O		0x0400000000000000ull
#define XCT_COPY_E		0x0200000000000000ull
#define XCT_COPY_STY_ZERO	0x01c0000000000000ull
#define XCT_COPY_DTY_PREF	0x0038000000000000ull
#define XCT_COPY_LLEN_M		0x0007ffff00000000ull
#define XCT_COPY_LLEN_S		32
#define XCT_COPY_LLEN(x)	((((long)(x)) << XCT_COPY_LLEN_S) & \
				 XCT_COPY_LLEN_M)
#define XCT_COPY_SE		0x0000000000000001ull

/* Function descriptor fields */
#define XCT_FUN_T		0x8000000000000000ull
#define XCT_FUN_ST		0x4000000000000000ull
#define XCT_FUN_RR_M		0x3000000000000000ull
#define XCT_FUN_RR_NORES	0x0000000000000000ull
#define XCT_FUN_RR_8BRES	0x1000000000000000ull
#define XCT_FUN_RR_24BRES	0x2000000000000000ull
#define XCT_FUN_RR_40BRES	0x3000000000000000ull
#define XCT_FUN_I		0x0800000000000000ull
#define XCT_FUN_O		0x0400000000000000ull
#define XCT_FUN_E		0x0200000000000000ull
#define XCT_FUN_FUN_M		0x01c0000000000000ull
#define XCT_FUN_FUN_S		54
#define XCT_FUN_FUN(x)		((((long)(x)) << XCT_FUN_FUN_S) & XCT_FUN_FUN_M)
#define XCT_FUN_CRM_M		0x0038000000000000ull
#define XCT_FUN_CRM_NOP		0x0000000000000000ull
#define XCT_FUN_CRM_SIG		0x0008000000000000ull
#define XCT_FUN_LLEN_M		0x0007ffff00000000ull
#define XCT_FUN_LLEN_S		32
#define XCT_FUN_LLEN(x)		((((long)(x)) << XCT_FUN_LLEN_S) & XCT_FUN_LLEN_M)
#define XCT_FUN_SHL_M		0x00000000f8000000ull
#define XCT_FUN_SHL_S		27
#define XCT_FUN_SHL(x)		((((long)(x)) << XCT_FUN_SHL_S) & XCT_FUN_SHL_M)
#define XCT_FUN_CHL_M		0x0000000007c00000ull
#define XCT_FUN_HSZ_M		0x00000000003c0000ull
#define XCT_FUN_ALG_M		0x0000000000038000ull
#define XCT_FUN_HP		0x0000000000004000ull
#define XCT_FUN_BCM_M		0x0000000000003800ull
#define XCT_FUN_BCP_M		0x0000000000000600ull
#define XCT_FUN_SIG_M		0x00000000000001f0ull
#define XCT_FUN_SIG_TCP4	0x0000000000000140ull
#define XCT_FUN_SIG_TCP6	0x0000000000000150ull
#define XCT_FUN_SIG_UDP4	0x0000000000000160ull
#define XCT_FUN_SIG_UDP6	0x0000000000000170ull
#define XCT_FUN_A		0x0000000000000008ull
#define XCT_FUN_C		0x0000000000000004ull
#define XCT_FUN_AL2		0x0000000000000002ull
#define XCT_FUN_SE		0x0000000000000001ull

/* Function descriptor 8byte result fields */
#define XCT_FUNRES_8B_CS_M	0x0000ffff00000000ull
#define XCT_FUNRES_8B_CS_S	32
#define XCT_FUNRES_8B_CRC_M	0x00000000ffffffffull
#define XCT_FUNRES_8B_CRC_S	0

/* Control descriptor fields */
#define CTRL_CMD_T		0x8000000000000000ull
#define CTRL_CMD_META_EVT	0x2000000000000000ull
#define CTRL_CMD_O		0x0400000000000000ull
#define CTRL_CMD_ETYPE_M	0x0038000000000000ull
#define CTRL_CMD_ETYPE_EXT	0x0000000000000000ull
#define CTRL_CMD_ETYPE_WSET	0x0020000000000000ull
#define CTRL_CMD_ETYPE_WCLR	0x0028000000000000ull
#define CTRL_CMD_ETYPE_SET	0x0030000000000000ull
#define CTRL_CMD_ETYPE_CLR	0x0038000000000000ull
#define CTRL_CMD_REG_M		0x000000000000007full
#define CTRL_CMD_REG_S		0
#define CTRL_CMD_REG(x)		((((long)(x)) << CTRL_CMD_REG_S) & \
				 CTRL_CMD_REG_M)



/* Prototypes for the shared DMA functions in the platform code. */

/* DMA TX Channel type. Right now only limitations used are event types 0/1,
 * for event-triggered DMA transactions.
 */

enum pasemi_dmachan_type {
	RXCHAN = 0,		/* Any RX chan */
	TXCHAN = 1,		/* Any TX chan */
	TXCHAN_EVT0 = 0x1001,	/* TX chan in event class 0 (chan 0-9) */
	TXCHAN_EVT1 = 0x2001,	/* TX chan in event class 1 (chan 10-19) */
};

struct pasemi_dmachan {
	int		 chno;		/* Channel number */
	enum pasemi_dmachan_type chan_type;	/* TX / RX */
	u64		*status;	/* Ptr to cacheable status */
	int		 irq;		/* IRQ used by channel */
	unsigned int	 ring_size;	/* size of allocated ring */
	dma_addr_t	 ring_dma;	/* DMA address for ring */
	u64		*ring_virt;	/* Virt address for ring */
	void		*priv;		/* Ptr to start of client struct */
};

/* Read/write the different registers in the I/O Bridge, Ethernet
 * and DMA Controller
 */
extern unsigned int pasemi_read_iob_reg(unsigned int reg);
extern void pasemi_write_iob_reg(unsigned int reg, unsigned int val);

extern unsigned int pasemi_read_mac_reg(int intf, unsigned int reg);
extern void pasemi_write_mac_reg(int intf, unsigned int reg, unsigned int val);

extern unsigned int pasemi_read_dma_reg(unsigned int reg);
extern void pasemi_write_dma_reg(unsigned int reg, unsigned int val);

/* Channel management routines */

extern void *pasemi_dma_alloc_chan(enum pasemi_dmachan_type type,
				   int total_size, int offset);
extern void pasemi_dma_free_chan(struct pasemi_dmachan *chan);

extern void pasemi_dma_start_chan(const struct pasemi_dmachan *chan,
				  const u32 cmdsta);
extern int pasemi_dma_stop_chan(const struct pasemi_dmachan *chan);

/* Common routines to allocate rings and buffers */

extern int pasemi_dma_alloc_ring(struct pasemi_dmachan *chan, int ring_size);
extern void pasemi_dma_free_ring(struct pasemi_dmachan *chan);

extern void *pasemi_dma_alloc_buf(struct pasemi_dmachan *chan, int size,
				  dma_addr_t *handle);
extern void pasemi_dma_free_buf(struct pasemi_dmachan *chan, int size,
				dma_addr_t *handle);

/* Routines to allocate flags (events) for channel synchronization */
extern int  pasemi_dma_alloc_flag(void);
extern void pasemi_dma_free_flag(int flag);
extern void pasemi_dma_set_flag(int flag);
extern void pasemi_dma_clear_flag(int flag);

/* Routines to allocate function engines */
extern int  pasemi_dma_alloc_fun(void);
extern void pasemi_dma_free_fun(int fun);

/* Initialize the library, must be called before any other functions */
extern int pasemi_dma_init(void);

#endif /* ASM_PASEMI_DMA_H */

Filemanager

Name Type Size Permission Actions
book3s Folder 0755
nohash Folder 0755
vdso Folder 0755
8xx_immap.h File 13.81 KB 0644
Kbuild File 262 B 0644
accounting.h File 908 B 0644
archrandom.h File 417 B 0644
asm-compat.h File 1.94 KB 0644
asm-const.h File 443 B 0644
asm-offsets.h File 35 B 0644
asm-prototypes.h File 2.17 KB 0644
asm.h File 154 B 0644
async_tx.h File 908 B 0644
atomic.h File 11.55 KB 0644
backlight.h File 1.02 KB 0644
barrier.h File 3.95 KB 0644
bitops.h File 9.13 KB 0644
bootx.h File 1.12 KB 0644
bpf_perf_event.h File 233 B 0644
btext.h File 1006 B 0644
bug.h File 3.23 KB 0644
cache.h File 2.9 KB 0644
cacheflush.h File 3.91 KB 0644
cell-pmu.h File 3.41 KB 0644
cell-regs.h File 9.57 KB 0644
checksum.h File 5.73 KB 0644
clocksource.h File 185 B 0644
cmpxchg.h File 16.28 KB 0644
code-patching-asm.h File 397 B 0644
compat.h File 2.5 KB 0644
context_tracking.h File 250 B 0644
copro.h File 593 B 0644
cpm.h File 25 B 0644
cpm1.h File 21.06 KB 0644
cpm2.h File 48.4 KB 0644
cpu_has_feature.h File 1.31 KB 0644
cpu_setup.h File 2.48 KB 0644
cpufeature.h File 1.04 KB 0644
cpuidle.h File 3.33 KB 0644
cputable.h File 23.17 KB 0644
cputhreads.h File 2.83 KB 0644
cputime.h File 2.22 KB 0644
crashdump-ppc64.h File 624 B 0644
current.h File 680 B 0644
dbdma.h File 3.72 KB 0644
dbell.h File 3.93 KB 0644
dcr-generic.h File 930 B 0644
dcr-mmio.h File 1 KB 0644
dcr-native.h File 3.77 KB 0644
dcr-regs.h File 5.71 KB 0644
dcr.h File 2.06 KB 0644
debug.h File 1.9 KB 0644
delay.h File 3.22 KB 0644
device.h File 1.09 KB 0644
disassemble.h File 2.14 KB 0644
dma-direct.h File 391 B 0644
dma.h File 10.38 KB 0644
drmem.h File 2.94 KB 0644
dt_cpu_ftrs.h File 756 B 0644
dtl.h File 1.06 KB 0644
edac.h File 1.08 KB 0644
eeh.h File 14.79 KB 0644
eeh_event.h File 826 B 0644
ehv_pic.h File 963 B 0644
elf.h File 6.48 KB 0644
elfnote.h File 527 B 0644
emergency-restart.h File 43 B 0644
emulated_ops.h File 2.02 KB 0644
epapr_hcalls.h File 16.43 KB 0644
exception-64e.h File 5.72 KB 0644
exception-64s.h File 4.25 KB 0644
exec.h File 246 B 0644
extable.h File 1.18 KB 0644
fadump-internal.h File 5.35 KB 0644
fadump.h File 1.38 KB 0644
feature-fixups.h File 9.7 KB 0644
firmware.h File 5.47 KB 0644
fixmap.h File 3.46 KB 0644
floppy.h File 5.01 KB 0644
fpu.h File 509 B 0644
fsl_gtm.h File 1.17 KB 0644
fsl_hcalls.h File 17.2 KB 0644
fsl_lbc.h File 10.24 KB 0644
fsl_pamu_stash.h File 411 B 0644
fsl_pm.h File 1.16 KB 0644
ftrace.h File 5.08 KB 0644
futex.h File 2.19 KB 0644
grackle.h File 331 B 0644
guest-state-buffer.h File 27.38 KB 0644
hardirq.h File 948 B 0644
head-64.h File 5.36 KB 0644
heathrow.h File 2.53 KB 0644
highmem.h File 2.03 KB 0644
hmi.h File 971 B 0644
hugetlb.h File 2.3 KB 0644
hvcall.h File 22.61 KB 0644
hvconsole.h File 800 B 0644
hvcserver.h File 1.44 KB 0644
hvsi.h File 2.83 KB 0644
hw_breakpoint.h File 3.69 KB 0644
hw_irq.h File 12.64 KB 0644
hydra.h File 2.88 KB 0644
i8259.h File 361 B 0644
ibmebus.h File 2.18 KB 0644
icswx.h File 4.97 KB 0644
idle.h File 2.37 KB 0644
imc-pmu.h File 3.91 KB 0644
immap_cpm2.h File 10.5 KB 0644
inst.h File 3.9 KB 0644
interrupt.h File 20.21 KB 0644
io-defs.h File 3.09 KB 0644
io-workarounds.h File 1.28 KB 0644
io.h File 30.97 KB 0644
io_event_irq.h File 1.71 KB 0644
iommu.h File 10.19 KB 0644
ipic.h File 3.07 KB 0644
irq.h File 1.33 KB 0644
irq_work.h File 213 B 0644
irqflags.h File 239 B 0644
isa-bridge.h File 654 B 0644
jump_label.h File 1.3 KB 0644
kasan.h File 2.27 KB 0644
kdebug.h File 291 B 0644
kdump.h File 1.37 KB 0644
kexec.h File 6 KB 0644
kexec_ranges.h File 743 B 0644
keylargo.h File 10.8 KB 0644
kfence.h File 1.16 KB 0644
kgdb.h File 2.11 KB 0644
kprobes.h File 2.64 KB 0644
kup.h File 4.21 KB 0644
kvm_asm.h File 4.89 KB 0644
kvm_book3s.h File 23.17 KB 0644
kvm_book3s_32.h File 816 B 0644
kvm_book3s_64.h File 18.78 KB 0644
kvm_book3s_asm.h File 3.56 KB 0644
kvm_book3s_uvmem.h File 2.67 KB 0644
kvm_booke.h File 2.41 KB 0644
kvm_booke_hv_asm.h File 1.91 KB 0644
kvm_fpu.h File 2.15 KB 0644
kvm_guest.h File 573 B 0644
kvm_host.h File 22.43 KB 0644
kvm_para.h File 752 B 0644
kvm_ppc.h File 37.63 KB 0644
libata-portmap.h File 249 B 0644
linkage.h File 508 B 0644
livepatch.h File 604 B 0644
local.h File 3.36 KB 0644
lppaca.h File 4.53 KB 0644
lv1call.h File 18.12 KB 0644
machdep.h File 8.74 KB 0644
macio.h File 3.93 KB 0644
mc146818rtc.h File 736 B 0644
mce.h File 6.58 KB 0644
mediabay.h File 1.34 KB 0644
mem_encrypt.h File 456 B 0644
membarrier.h File 877 B 0644
mman.h File 1.11 KB 0644
mmiowb.h File 374 B 0644
mmu.h File 10.63 KB 0644
mmu_context.h File 8.67 KB 0644
mmzone.h File 902 B 0644
module.h File 2.38 KB 0644
module.lds.h File 95 B 0644
mpc5121.h File 3.77 KB 0644
mpc52xx.h File 9.76 KB 0644
mpc52xx_psc.h File 9.89 KB 0644
mpc5xxx.h File 610 B 0644
mpc6xx.h File 143 B 0644
mpc85xx.h File 2.33 KB 0644
mpic.h File 13.98 KB 0644
mpic_msgr.h File 3.36 KB 0644
mpic_timer.h File 1.16 KB 0644
msi_bitmap.h File 867 B 0644
nmi.h File 372 B 0644
nvram.h File 2.77 KB 0644
ohare.h File 1.64 KB 0644
opal-api.h File 30.97 KB 0644
opal.h File 17.01 KB 0644
paca.h File 8.66 KB 0644
page.h File 8.64 KB 0644
page_32.h File 1.51 KB 0644
page_64.h File 2.65 KB 0644
papr-sysparm.h File 1.51 KB 0644
paravirt.h File 6.18 KB 0644
paravirt_api_clock.h File 65 B 0644
parport.h File 960 B 0644
pasemi_dma.h File 22.73 KB 0644
pci-bridge.h File 9.36 KB 0644
pci.h File 3.51 KB 0644
percpu.h File 782 B 0644
perf_event.h File 1.47 KB 0644
perf_event_fsl_emb.h File 1.22 KB 0644
perf_event_server.h File 7.01 KB 0644
pgalloc.h File 2.2 KB 0644
pgtable-be-types.h File 2.37 KB 0644
pgtable-masks.h File 1.11 KB 0644
pgtable-types.h File 2.23 KB 0644
pgtable.h File 5.99 KB 0644
pkeys.h File 4.18 KB 0644
plpar_wrappers.h File 14.62 KB 0644
plpks.h File 5.09 KB 0644
pmac_feature.h File 13.35 KB 0644
pmac_low_i2c.h File 3.03 KB 0644
pmac_pfunc.h File 8.04 KB 0644
pmc.h File 1.09 KB 0644
pmi.h File 1.15 KB 0644
pnv-ocxl.h File 3 KB 0644
pnv-pci.h File 2.4 KB 0644
powernv.h File 454 B 0644
ppc-opcode.h File 32.59 KB 0644
ppc-pci.h File 2.77 KB 0644
ppc4xx.h File 328 B 0644
ppc_asm.h File 23.13 KB 0644
probes.h File 2.46 KB 0644
processor.h File 13.06 KB 0644
prom.h File 7 KB 0644
ps3.h File 14.84 KB 0644
ps3av.h File 22.81 KB 0644
ps3gpu.h File 1.88 KB 0644
ps3stor.h File 1.38 KB 0644
pte-walk.h File 1.52 KB 0644
ptrace.h File 11.81 KB 0644
qspinlock.h File 4.76 KB 0644
qspinlock_types.h File 1.59 KB 0644
reg.h File 63.24 KB 0644
reg_8xx.h File 2.8 KB 0644
reg_booke.h File 28.05 KB 0644
reg_fsl_emb.h File 3.94 KB 0644
rheap.h File 2.52 KB 0644
rio.h File 424 B 0644
rtas-types.h File 2.84 KB 0644
rtas-work-area.h File 2.75 KB 0644
rtas.h File 23.33 KB 0644
runlatch.h File 1.15 KB 0644
seccomp.h File 1.02 KB 0644
sections.h File 2.04 KB 0644
secure_boot.h File 476 B 0644
security_features.h File 3.43 KB 0644
secvar.h File 994 B 0644
serial.h File 473 B 0644
set_memory.h File 1.41 KB 0644
setjmp.h File 400 B 0644
setup.h File 2.79 KB 0644
sfp-machine.h File 12.38 KB 0644
shmparam.h File 206 B 0644
signal.h File 506 B 0644
simple_spinlock.h File 6.1 KB 0644
simple_spinlock_types.h File 487 B 0644
smp.h File 7.01 KB 0644
smu.h File 19.33 KB 0644
sparsemem.h File 843 B 0644
spinlock.h File 474 B 0644
spinlock_types.h File 380 B 0644
spu.h File 23.41 KB 0644
spu_csa.h File 6.02 KB 0644
spu_info.h File 272 B 0644
spu_priv1.h File 5.01 KB 0644
sstep.h File 4.6 KB 0644
stackprotector.h File 604 B 0644
stacktrace.h File 297 B 0644
static_call.h File 1.04 KB 0644
string.h File 2.8 KB 0644
svm.h File 591 B 0644
swab.h File 173 B 0644
swiotlb.h File 413 B 0644
switch_to.h File 3.15 KB 0644
synch.h File 2.11 KB 0644
syscall.h File 2.95 KB 0644
syscall_wrapper.h File 1.63 KB 0644
syscalls.h File 5.05 KB 0644
syscalls_32.h File 1.58 KB 0644
systemcfg.h File 1.69 KB 0644
task_size_32.h File 544 B 0644
task_size_64.h File 2.57 KB 0644
tce.h File 892 B 0644
text-patching.h File 7.37 KB 0644
thread_info.h File 7.7 KB 0644
time.h File 2.92 KB 0644
timex.h File 463 B 0644
tlb.h File 2.3 KB 0644
tlbflush.h File 271 B 0644
tm.h File 624 B 0644
topology.h File 4.07 KB 0644
trace.h File 7.26 KB 0644
trace_clock.h File 372 B 0644
tsi108.h File 3.19 KB 0644
tsi108_irq.h File 3.82 KB 0644
tsi108_pci.h File 1.16 KB 0644
types.h File 573 B 0644
uaccess.h File 14.44 KB 0644
udbg.h File 1.7 KB 0644
uic.h File 403 B 0644
ultravisor-api.h File 941 B 0644
ultravisor.h File 2.05 KB 0644
uninorth.h File 8.21 KB 0644
unistd.h File 1.45 KB 0644
uprobes.h File 770 B 0644
user.h File 1.95 KB 0644
vas.h File 7.91 KB 0644
vdso.h File 1022 B 0644
vdso_datapage.h File 1.72 KB 0644
vermagic.h File 612 B 0644
vga.h File 1.13 KB 0644
video.h File 431 B 0644
vio.h File 4.54 KB 0644
vmalloc.h File 554 B 0644
vphn.h File 802 B 0644
word-at-a-time.h File 4.79 KB 0644
xics.h File 4.39 KB 0644
xive-regs.h File 4.96 KB 0644
xive.h File 5.07 KB 0644
xmon.h File 733 B 0644
xor.h File 1017 B 0644
xor_altivec.h File 888 B 0644
Filemanager