__  __    __   __  _____      _            _          _____ _          _ _ 
 |  \/  |   \ \ / / |  __ \    (_)          | |        / ____| |        | | |
 | \  / |_ __\ V /  | |__) | __ ___   ____ _| |_ ___  | (___ | |__   ___| | |
 | |\/| | '__|> <   |  ___/ '__| \ \ / / _` | __/ _ \  \___ \| '_ \ / _ \ | |
 | |  | | |_ / . \  | |   | |  | |\ V / (_| | ||  __/  ____) | | | |  __/ | |
 |_|  |_|_(_)_/ \_\ |_|   |_|  |_| \_/ \__,_|\__\___| |_____/|_| |_|\___V 2.1
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/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 2003, 2004 Ralf Baechle
 * Copyright (C) 2004  Maciej W. Rozycki
 */
#ifndef __ASM_CPU_FEATURES_H
#define __ASM_CPU_FEATURES_H

#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <asm/isa-rev.h>
#include <cpu-feature-overrides.h>

#define __ase(ase)			(cpu_data[0].ases & (ase))
#define __isa(isa)			(cpu_data[0].isa_level & (isa))
#define __opt(opt)			(cpu_data[0].options & (opt))

/*
 * Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during
 * boot (typically by cpu_probe()).
 *
 * Note that these should only be used in cases where a kernel built for an
 * older ISA *cannot* run on a CPU which supports the feature in question. For
 * example this may be used for features introduced with MIPSr6, since a kernel
 * built for an older ISA cannot run on a MIPSr6 CPU. This should not be used
 * for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a
 * MIPSr2 CPU.
 */
#define __isa_ge_and_ase(isa, ase)	((MIPS_ISA_REV >= (isa)) && __ase(ase))
#define __isa_ge_and_opt(isa, opt)	((MIPS_ISA_REV >= (isa)) && __opt(opt))

/*
 * Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during
 * boot (typically by cpu_probe()).
 *
 * These are for use with features that are optional up until a particular ISA
 * revision & then become required.
 */
#define __isa_ge_or_ase(isa, ase)	((MIPS_ISA_REV >= (isa)) || __ase(ase))
#define __isa_ge_or_opt(isa, opt)	((MIPS_ISA_REV >= (isa)) || __opt(opt))

/*
 * Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during
 * boot (typically by cpu_probe()).
 *
 * These are for use with features that are optional up until a particular ISA
 * revision & are then removed - ie. no longer present in any CPU implementing
 * the given ISA revision.
 */
#define __isa_lt_and_ase(isa, ase)	((MIPS_ISA_REV < (isa)) && __ase(ase))
#define __isa_lt_and_opt(isa, opt)	((MIPS_ISA_REV < (isa)) && __opt(opt))

/*
 * Similarly allow for ISA level checks that take into account knowledge of the
 * ISA targeted by the kernel build, provided by MIPS_ISA_REV.
 */
#define __isa_ge_and_flag(isa, flag)	((MIPS_ISA_REV >= (isa)) && __isa(flag))
#define __isa_ge_or_flag(isa, flag)	((MIPS_ISA_REV >= (isa)) || __isa(flag))
#define __isa_lt_and_flag(isa, flag)	((MIPS_ISA_REV < (isa)) && __isa(flag))
#define __isa_range(ge, lt) \
	((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt)))
#define __isa_range_or_flag(ge, lt, flag) \
	(__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag)))
#define __isa_range_and_ase(ge, lt, ase) \
	(__isa_range(ge, lt) && __ase(ase))

/*
 * SMP assumption: Options of CPU 0 are a superset of all processors.
 * This is true for all known MIPS systems.
 */
#ifndef cpu_has_tlb
#define cpu_has_tlb		__opt(MIPS_CPU_TLB)
#endif
#ifndef cpu_has_ftlb
#define cpu_has_ftlb		__opt(MIPS_CPU_FTLB)
#endif
#ifndef cpu_has_tlbinv
#define cpu_has_tlbinv		__opt(MIPS_CPU_TLBINV)
#endif
#ifndef cpu_has_segments
#define cpu_has_segments	__opt(MIPS_CPU_SEGMENTS)
#endif
#ifndef cpu_has_eva
#define cpu_has_eva		__opt(MIPS_CPU_EVA)
#endif
#ifndef cpu_has_htw
#define cpu_has_htw		__opt(MIPS_CPU_HTW)
#endif
#ifndef cpu_has_ldpte
#define cpu_has_ldpte		__opt(MIPS_CPU_LDPTE)
#endif
#ifndef cpu_has_rixiex
#define cpu_has_rixiex		__isa_ge_or_opt(6, MIPS_CPU_RIXIEX)
#endif
#ifndef cpu_has_maar
#define cpu_has_maar		__opt(MIPS_CPU_MAAR)
#endif
#ifndef cpu_has_rw_llb
#define cpu_has_rw_llb		__isa_ge_or_opt(6, MIPS_CPU_RW_LLB)
#endif

/*
 * For the moment we don't consider R6000 and R8000 so we can assume that
 * anything that doesn't support R4000-style exceptions and interrupts is
 * R3000-like.  Users should still treat these two macro definitions as
 * opaque.
 */
#ifndef cpu_has_3kex
#define cpu_has_3kex		(!cpu_has_4kex)
#endif
#ifndef cpu_has_4kex
#define cpu_has_4kex		__isa_ge_or_opt(1, MIPS_CPU_4KEX)
#endif
#ifndef cpu_has_3k_cache
#define cpu_has_3k_cache	__isa_lt_and_opt(1, MIPS_CPU_3K_CACHE)
#endif
#ifndef cpu_has_4k_cache
#define cpu_has_4k_cache	__opt(MIPS_CPU_4K_CACHE)
#endif
#ifndef cpu_has_octeon_cache
#define cpu_has_octeon_cache						\
({									\
	int __res;							\
									\
	switch (boot_cpu_type()) {					\
	case CPU_CAVIUM_OCTEON:						\
	case CPU_CAVIUM_OCTEON_PLUS:					\
	case CPU_CAVIUM_OCTEON2:					\
	case CPU_CAVIUM_OCTEON3:					\
		__res = 1;						\
		break;							\
									\
	default:							\
		__res = 0;						\
	}								\
									\
	__res;								\
})
#endif
/* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work.  */
#ifndef cpu_has_fpu
# ifdef CONFIG_MIPS_FP_SUPPORT
#  define cpu_has_fpu		(current_cpu_data.options & MIPS_CPU_FPU)
#  define raw_cpu_has_fpu	(raw_current_cpu_data.options & MIPS_CPU_FPU)
# else
#  define cpu_has_fpu		0
#  define raw_cpu_has_fpu	0
# endif
#else
# if cpu_has_fpu
#  error "Forcing `cpu_has_fpu' to non-zero is not supported"
# endif
# define raw_cpu_has_fpu	cpu_has_fpu
#endif
#ifndef cpu_has_32fpr
#define cpu_has_32fpr		__isa_ge_or_opt(1, MIPS_CPU_32FPR)
#endif
#ifndef cpu_has_counter
#define cpu_has_counter		__opt(MIPS_CPU_COUNTER)
#endif
#ifndef cpu_has_watch
#define cpu_has_watch		__opt(MIPS_CPU_WATCH)
#endif
#ifndef cpu_has_divec
#define cpu_has_divec		__isa_ge_or_opt(1, MIPS_CPU_DIVEC)
#endif
#ifndef cpu_has_vce
#define cpu_has_vce		__opt(MIPS_CPU_VCE)
#endif
#ifndef cpu_has_cache_cdex_p
#define cpu_has_cache_cdex_p	__opt(MIPS_CPU_CACHE_CDEX_P)
#endif
#ifndef cpu_has_cache_cdex_s
#define cpu_has_cache_cdex_s	__opt(MIPS_CPU_CACHE_CDEX_S)
#endif
#ifndef cpu_has_prefetch
#define cpu_has_prefetch	__isa_ge_or_opt(1, MIPS_CPU_PREFETCH)
#endif
#ifndef cpu_has_mcheck
#define cpu_has_mcheck		__isa_ge_or_opt(1, MIPS_CPU_MCHECK)
#endif
#ifndef cpu_has_ejtag
#define cpu_has_ejtag		__opt(MIPS_CPU_EJTAG)
#endif
#ifndef cpu_has_llsc
#define cpu_has_llsc		__isa_ge_or_opt(1, MIPS_CPU_LLSC)
#endif
#ifndef kernel_uses_llsc
#define kernel_uses_llsc	cpu_has_llsc
#endif
#ifndef cpu_has_guestctl0ext
#define cpu_has_guestctl0ext	__opt(MIPS_CPU_GUESTCTL0EXT)
#endif
#ifndef cpu_has_guestctl1
#define cpu_has_guestctl1	__opt(MIPS_CPU_GUESTCTL1)
#endif
#ifndef cpu_has_guestctl2
#define cpu_has_guestctl2	__opt(MIPS_CPU_GUESTCTL2)
#endif
#ifndef cpu_has_guestid
#define cpu_has_guestid		__opt(MIPS_CPU_GUESTID)
#endif
#ifndef cpu_has_drg
#define cpu_has_drg		__opt(MIPS_CPU_DRG)
#endif
#ifndef cpu_has_mips16
#define cpu_has_mips16		__isa_lt_and_ase(6, MIPS_ASE_MIPS16)
#endif
#ifndef cpu_has_mips16e2
#define cpu_has_mips16e2	__isa_lt_and_ase(6, MIPS_ASE_MIPS16E2)
#endif
#ifndef cpu_has_mdmx
#define cpu_has_mdmx		__isa_lt_and_ase(6, MIPS_ASE_MDMX)
#endif
#ifndef cpu_has_mips3d
#define cpu_has_mips3d		__isa_lt_and_ase(6, MIPS_ASE_MIPS3D)
#endif
#ifndef cpu_has_smartmips
#define cpu_has_smartmips	__isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS)
#endif

#ifndef cpu_has_rixi
#define cpu_has_rixi		__isa_ge_or_opt(6, MIPS_CPU_RIXI)
#endif

#ifndef cpu_has_mmips
# if defined(__mips_micromips)
#  define cpu_has_mmips		1
# elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
#  define cpu_has_mmips		__opt(MIPS_CPU_MICROMIPS)
# else
#  define cpu_has_mmips		0
# endif
#endif

#ifndef cpu_has_lpa
#define cpu_has_lpa		__opt(MIPS_CPU_LPA)
#endif
#ifndef cpu_has_mvh
#define cpu_has_mvh		__opt(MIPS_CPU_MVH)
#endif
#ifndef cpu_has_xpa
#define cpu_has_xpa		(cpu_has_lpa && cpu_has_mvh)
#endif
#ifndef cpu_has_vtag_icache
#define cpu_has_vtag_icache	(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
#endif
#ifndef cpu_has_dc_aliases
#define cpu_has_dc_aliases	(cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
#endif
#ifndef cpu_has_ic_fills_f_dc
#define cpu_has_ic_fills_f_dc	(cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
#endif
#ifndef cpu_has_pindexed_dcache
#define cpu_has_pindexed_dcache	(cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
#endif

/*
 * I-Cache snoops remote store.	 This only matters on SMP.  Some multiprocessors
 * such as the R10000 have I-Caches that snoop local stores; the embedded ones
 * don't.  For maintaining I-cache coherency this means we need to flush the
 * D-cache all the way back to whever the I-cache does refills from, so the
 * I-cache has a chance to see the new data at all.  Then we have to flush the
 * I-cache also.
 * Note we may have been rescheduled and may no longer be running on the CPU
 * that did the store so we can't optimize this into only doing the flush on
 * the local CPU.
 */
#ifndef cpu_icache_snoops_remote_store
#ifdef CONFIG_SMP
#define cpu_icache_snoops_remote_store	(cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
#else
#define cpu_icache_snoops_remote_store	1
#endif
#endif

#ifndef cpu_has_mips_1
# define cpu_has_mips_1		(MIPS_ISA_REV < 6)
#endif
#ifndef cpu_has_mips_2
# define cpu_has_mips_2		__isa_lt_and_flag(6, MIPS_CPU_ISA_II)
#endif
#ifndef cpu_has_mips_3
# define cpu_has_mips_3		__isa_lt_and_flag(6, MIPS_CPU_ISA_III)
#endif
#ifndef cpu_has_mips_4
# define cpu_has_mips_4		__isa_lt_and_flag(6, MIPS_CPU_ISA_IV)
#endif
#ifndef cpu_has_mips_5
# define cpu_has_mips_5		__isa_lt_and_flag(6, MIPS_CPU_ISA_V)
#endif
#ifndef cpu_has_mips32r1
# define cpu_has_mips32r1	__isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1)
#endif
#ifndef cpu_has_mips32r2
# define cpu_has_mips32r2	__isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2)
#endif
#ifndef cpu_has_mips32r5
# define cpu_has_mips32r5	__isa_range_or_flag(5, 6, MIPS_CPU_ISA_M32R5)
#endif
#ifndef cpu_has_mips32r6
# define cpu_has_mips32r6	__isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6)
#endif
#ifndef cpu_has_mips64r1
# define cpu_has_mips64r1	(cpu_has_64bits && \
				 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1))
#endif
#ifndef cpu_has_mips64r2
# define cpu_has_mips64r2	(cpu_has_64bits && \
				 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2))
#endif
#ifndef cpu_has_mips64r5
# define cpu_has_mips64r5	(cpu_has_64bits && \
				 __isa_range_or_flag(5, 6, MIPS_CPU_ISA_M64R5))
#endif
#ifndef cpu_has_mips64r6
# define cpu_has_mips64r6	__isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6)
#endif

/*
 * Shortcuts ...
 */
#define cpu_has_mips_2_3_4_5	(cpu_has_mips_2 | cpu_has_mips_3_4_5)
#define cpu_has_mips_3_4_5	(cpu_has_mips_3 | cpu_has_mips_4_5)
#define cpu_has_mips_4_5	(cpu_has_mips_4 | cpu_has_mips_5)

#define cpu_has_mips_2_3_4_5_r	(cpu_has_mips_2 | cpu_has_mips_3_4_5_r)
#define cpu_has_mips_3_4_5_r	(cpu_has_mips_3 | cpu_has_mips_4_5_r)
#define cpu_has_mips_4_5_r	(cpu_has_mips_4 | cpu_has_mips_5_r)
#define cpu_has_mips_5_r	(cpu_has_mips_5 | cpu_has_mips_r)

#define cpu_has_mips_3_4_5_64_r2_r6					\
				(cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6)
#define cpu_has_mips_4_5_64_r2_r6					\
				(cpu_has_mips_4_5 | cpu_has_mips64r1 |	\
				 cpu_has_mips_r2 | cpu_has_mips_r5 | \
				 cpu_has_mips_r6)

#define cpu_has_mips32	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
			 cpu_has_mips32r5 | cpu_has_mips32r6)
#define cpu_has_mips64	(cpu_has_mips64r1 | cpu_has_mips64r2 | \
			 cpu_has_mips64r5 | cpu_has_mips64r6)
#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
#define cpu_has_mips_r5	(cpu_has_mips32r5 | cpu_has_mips64r5)
#define cpu_has_mips_r6	(cpu_has_mips32r6 | cpu_has_mips64r6)
#define cpu_has_mips_r	(cpu_has_mips32r1 | cpu_has_mips32r2 | \
			 cpu_has_mips32r5 | cpu_has_mips32r6 | \
			 cpu_has_mips64r1 | cpu_has_mips64r2 | \
			 cpu_has_mips64r5 | cpu_has_mips64r6)

/* MIPSR2 - MIPSR6 have a lot of similarities */
#define cpu_has_mips_r2_r6	(cpu_has_mips_r2 | cpu_has_mips_r5 | \
				 cpu_has_mips_r6)

/*
 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor
 *
 * Returns non-zero value if the current processor implementation requires
 * an IHB instruction to deal with an instruction hazard as per MIPS R2
 * architecture specification, zero otherwise.
 */
#ifndef cpu_has_mips_r2_exec_hazard
#define cpu_has_mips_r2_exec_hazard					\
({									\
	int __res;							\
									\
	switch (boot_cpu_type()) {					\
	case CPU_M14KC:							\
	case CPU_74K:							\
	case CPU_1074K:							\
	case CPU_PROAPTIV:						\
	case CPU_P5600:							\
	case CPU_M5150:							\
	case CPU_QEMU_GENERIC:						\
	case CPU_CAVIUM_OCTEON:						\
	case CPU_CAVIUM_OCTEON_PLUS:					\
	case CPU_CAVIUM_OCTEON2:					\
	case CPU_CAVIUM_OCTEON3:					\
		__res = 0;						\
		break;							\
									\
	default:							\
		__res = 1;						\
	}								\
									\
	__res;								\
})
#endif

/*
 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
 * pre-MIPS32/MIPS64 processors have CLO, CLZ.	The IDT RC64574 is 64-bit and
 * has CLO and CLZ but not DCLO nor DCLZ.  For 64-bit kernels
 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
 */
#ifndef cpu_has_clo_clz
#define cpu_has_clo_clz	cpu_has_mips_r
#endif

/*
 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
 * This indicates the availability of WSBH and in case of 64 bit CPUs also
 * DSBH and DSHD.
 */
#ifndef cpu_has_wsbh
#define cpu_has_wsbh		cpu_has_mips_r2
#endif

#ifndef cpu_has_dsp
#define cpu_has_dsp		__ase(MIPS_ASE_DSP)
#endif

#ifndef cpu_has_dsp2
#define cpu_has_dsp2		__ase(MIPS_ASE_DSP2P)
#endif

#ifndef cpu_has_dsp3
#define cpu_has_dsp3		__ase(MIPS_ASE_DSP3)
#endif

#ifndef cpu_has_loongson_mmi
#define cpu_has_loongson_mmi		__ase(MIPS_ASE_LOONGSON_MMI)
#endif

#ifndef cpu_has_loongson_cam
#define cpu_has_loongson_cam		__ase(MIPS_ASE_LOONGSON_CAM)
#endif

#ifndef cpu_has_loongson_ext
#define cpu_has_loongson_ext		__ase(MIPS_ASE_LOONGSON_EXT)
#endif

#ifndef cpu_has_loongson_ext2
#define cpu_has_loongson_ext2		__ase(MIPS_ASE_LOONGSON_EXT2)
#endif

#ifndef cpu_has_mipsmt
#define cpu_has_mipsmt		__isa_range_and_ase(2, 6, MIPS_ASE_MIPSMT)
#endif

#ifndef cpu_has_vp
#define cpu_has_vp		__isa_ge_and_opt(6, MIPS_CPU_VP)
#endif

#ifndef cpu_has_userlocal
#define cpu_has_userlocal	__isa_ge_or_opt(6, MIPS_CPU_ULRI)
#endif

#ifdef CONFIG_32BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex	__isa_lt_and_opt(1, MIPS_CPU_NOFPUEX)
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits		(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg	(cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs		0
# endif
# ifndef cpu_vmbits
# define cpu_vmbits 31
# endif
#endif

#ifdef CONFIG_64BIT
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex		0
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits			1
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg		1
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs		1
# endif
# ifndef cpu_vmbits
# define cpu_vmbits cpu_data[0].vmbits
# define __NEED_VMBITS_PROBE
# endif
#endif

#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
# define cpu_has_vint		__opt(MIPS_CPU_VINT)
#elif !defined(cpu_has_vint)
# define cpu_has_vint			0
#endif

#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
# define cpu_has_veic		__opt(MIPS_CPU_VEIC)
#elif !defined(cpu_has_veic)
# define cpu_has_veic			0
#endif

#ifndef cpu_has_inclusive_pcaches
#define cpu_has_inclusive_pcaches	__opt(MIPS_CPU_INCLUSIVE_CACHES)
#endif

#ifndef cpu_dcache_line_size
#define cpu_dcache_line_size()	cpu_data[0].dcache.linesz
#endif
#ifndef cpu_icache_line_size
#define cpu_icache_line_size()	cpu_data[0].icache.linesz
#endif
#ifndef cpu_scache_line_size
#define cpu_scache_line_size()	cpu_data[0].scache.linesz
#endif
#ifndef cpu_tcache_line_size
#define cpu_tcache_line_size()	cpu_data[0].tcache.linesz
#endif

#ifndef cpu_hwrena_impl_bits
#define cpu_hwrena_impl_bits		0
#endif

#ifndef cpu_has_perf_cntr_intr_bit
#define cpu_has_perf_cntr_intr_bit	__opt(MIPS_CPU_PCI)
#endif

#ifndef cpu_has_vz
#define cpu_has_vz		__ase(MIPS_ASE_VZ)
#endif

#if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa)
# define cpu_has_msa		__ase(MIPS_ASE_MSA)
#elif !defined(cpu_has_msa)
# define cpu_has_msa		0
#endif

#ifndef cpu_has_ufr
# define cpu_has_ufr		__opt(MIPS_CPU_UFR)
#endif

#ifndef cpu_has_fre
# define cpu_has_fre		__opt(MIPS_CPU_FRE)
#endif

#ifndef cpu_has_cdmm
# define cpu_has_cdmm		__opt(MIPS_CPU_CDMM)
#endif

#ifndef cpu_has_small_pages
# define cpu_has_small_pages	__opt(MIPS_CPU_SP)
#endif

#ifndef cpu_has_nan_legacy
#define cpu_has_nan_legacy	__isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY)
#endif
#ifndef cpu_has_nan_2008
#define cpu_has_nan_2008	__isa_ge_or_opt(6, MIPS_CPU_NAN_2008)
#endif

#ifndef cpu_has_ebase_wg
# define cpu_has_ebase_wg	__opt(MIPS_CPU_EBASE_WG)
#endif

#ifndef cpu_has_badinstr
# define cpu_has_badinstr	__isa_ge_or_opt(6, MIPS_CPU_BADINSTR)
#endif

#ifndef cpu_has_badinstrp
# define cpu_has_badinstrp	__isa_ge_or_opt(6, MIPS_CPU_BADINSTRP)
#endif

#ifndef cpu_has_contextconfig
# define cpu_has_contextconfig	__opt(MIPS_CPU_CTXTC)
#endif

#ifndef cpu_has_perf
# define cpu_has_perf		__opt(MIPS_CPU_PERF)
#endif

#ifndef cpu_has_mac2008_only
# define cpu_has_mac2008_only	__opt(MIPS_CPU_MAC_2008_ONLY)
#endif

#ifndef cpu_has_ftlbparex
# define cpu_has_ftlbparex	__opt(MIPS_CPU_FTLBPAREX)
#endif

#ifndef cpu_has_gsexcex
# define cpu_has_gsexcex	__opt(MIPS_CPU_GSEXCEX)
#endif

#ifdef CONFIG_SMP
/*
 * Some systems share FTLB RAMs between threads within a core (siblings in
 * kernel parlance). This means that FTLB entries may become invalid at almost
 * any point when an entry is evicted due to a sibling thread writing an entry
 * to the shared FTLB RAM.
 *
 * This is only relevant to SMP systems, and the only systems that exhibit this
 * property implement MIPSr6 or higher so we constrain support for this to
 * kernels that will run on such systems.
 */
# ifndef cpu_has_shared_ftlb_ram
#  define cpu_has_shared_ftlb_ram \
	__isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM)
# endif

/*
 * Some systems take this a step further & share FTLB entries between siblings.
 * This is implemented as TLB writes happening as usual, but if an entry
 * written by a sibling exists in the shared FTLB for a translation which would
 * otherwise cause a TLB refill exception then the CPU will use the entry
 * written by its sibling rather than triggering a refill & writing a matching
 * TLB entry for itself.
 *
 * This is naturally only valid if a TLB entry is known to be suitable for use
 * on all siblings in a CPU, and so it only takes effect when MMIDs are in use
 * rather than ASIDs or when a TLB entry is marked global.
 */
# ifndef cpu_has_shared_ftlb_entries
#  define cpu_has_shared_ftlb_entries \
	__isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES)
# endif
#endif /* SMP */

#ifndef cpu_has_shared_ftlb_ram
# define cpu_has_shared_ftlb_ram 0
#endif
#ifndef cpu_has_shared_ftlb_entries
# define cpu_has_shared_ftlb_entries 0
#endif

#ifdef CONFIG_MIPS_MT_SMP
# define cpu_has_mipsmt_pertccounters \
	__isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS)
#else
# define cpu_has_mipsmt_pertccounters 0
#endif /* CONFIG_MIPS_MT_SMP */

/*
 * We only enable MMID support for configurations which natively support 64 bit
 * atomics because getting good performance from the allocator relies upon
 * efficient atomic64_*() functions.
 */
#ifndef cpu_has_mmid
# ifdef CONFIG_GENERIC_ATOMIC64
#  define cpu_has_mmid		0
# else
#  define cpu_has_mmid		__isa_ge_and_opt(6, MIPS_CPU_MMID)
# endif
#endif

#ifndef cpu_has_mm_sysad
# define cpu_has_mm_sysad	__opt(MIPS_CPU_MM_SYSAD)
#endif

#ifndef cpu_has_mm_full
# define cpu_has_mm_full	__opt(MIPS_CPU_MM_FULL)
#endif

/*
 * Guest capabilities
 */
#ifndef cpu_guest_has_conf1
#define cpu_guest_has_conf1	(cpu_data[0].guest.conf & (1 << 1))
#endif
#ifndef cpu_guest_has_conf2
#define cpu_guest_has_conf2	(cpu_data[0].guest.conf & (1 << 2))
#endif
#ifndef cpu_guest_has_conf3
#define cpu_guest_has_conf3	(cpu_data[0].guest.conf & (1 << 3))
#endif
#ifndef cpu_guest_has_conf4
#define cpu_guest_has_conf4	(cpu_data[0].guest.conf & (1 << 4))
#endif
#ifndef cpu_guest_has_conf5
#define cpu_guest_has_conf5	(cpu_data[0].guest.conf & (1 << 5))
#endif
#ifndef cpu_guest_has_conf6
#define cpu_guest_has_conf6	(cpu_data[0].guest.conf & (1 << 6))
#endif
#ifndef cpu_guest_has_conf7
#define cpu_guest_has_conf7	(cpu_data[0].guest.conf & (1 << 7))
#endif
#ifndef cpu_guest_has_fpu
#define cpu_guest_has_fpu	(cpu_data[0].guest.options & MIPS_CPU_FPU)
#endif
#ifndef cpu_guest_has_watch
#define cpu_guest_has_watch	(cpu_data[0].guest.options & MIPS_CPU_WATCH)
#endif
#ifndef cpu_guest_has_contextconfig
#define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC)
#endif
#ifndef cpu_guest_has_segments
#define cpu_guest_has_segments	(cpu_data[0].guest.options & MIPS_CPU_SEGMENTS)
#endif
#ifndef cpu_guest_has_badinstr
#define cpu_guest_has_badinstr	(cpu_data[0].guest.options & MIPS_CPU_BADINSTR)
#endif
#ifndef cpu_guest_has_badinstrp
#define cpu_guest_has_badinstrp	(cpu_data[0].guest.options & MIPS_CPU_BADINSTRP)
#endif
#ifndef cpu_guest_has_htw
#define cpu_guest_has_htw	(cpu_data[0].guest.options & MIPS_CPU_HTW)
#endif
#ifndef cpu_guest_has_ldpte
#define cpu_guest_has_ldpte	(cpu_data[0].guest.options & MIPS_CPU_LDPTE)
#endif
#ifndef cpu_guest_has_mvh
#define cpu_guest_has_mvh	(cpu_data[0].guest.options & MIPS_CPU_MVH)
#endif
#ifndef cpu_guest_has_msa
#define cpu_guest_has_msa	(cpu_data[0].guest.ases & MIPS_ASE_MSA)
#endif
#ifndef cpu_guest_has_kscr
#define cpu_guest_has_kscr(n)	(cpu_data[0].guest.kscratch_mask & (1u << (n)))
#endif
#ifndef cpu_guest_has_rw_llb
#define cpu_guest_has_rw_llb	(cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB))
#endif
#ifndef cpu_guest_has_perf
#define cpu_guest_has_perf	(cpu_data[0].guest.options & MIPS_CPU_PERF)
#endif
#ifndef cpu_guest_has_maar
#define cpu_guest_has_maar	(cpu_data[0].guest.options & MIPS_CPU_MAAR)
#endif
#ifndef cpu_guest_has_userlocal
#define cpu_guest_has_userlocal	(cpu_data[0].guest.options & MIPS_CPU_ULRI)
#endif

/*
 * Guest dynamic capabilities
 */
#ifndef cpu_guest_has_dyn_fpu
#define cpu_guest_has_dyn_fpu	(cpu_data[0].guest.options_dyn & MIPS_CPU_FPU)
#endif
#ifndef cpu_guest_has_dyn_watch
#define cpu_guest_has_dyn_watch	(cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH)
#endif
#ifndef cpu_guest_has_dyn_contextconfig
#define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC)
#endif
#ifndef cpu_guest_has_dyn_perf
#define cpu_guest_has_dyn_perf	(cpu_data[0].guest.options_dyn & MIPS_CPU_PERF)
#endif
#ifndef cpu_guest_has_dyn_msa
#define cpu_guest_has_dyn_msa	(cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA)
#endif
#ifndef cpu_guest_has_dyn_maar
#define cpu_guest_has_dyn_maar	(cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR)
#endif

#endif /* __ASM_CPU_FEATURES_H */

Filemanager

DIR : / usr/ src/ linux-headers-6.14.0-36/ arch/ mips/ include/ asm/
Name Type Size Permission Actions
dec Folder 0755
fw Folder 0755
ip32 Folder 0755
mach-ath25 Folder 0755
mach-ath79 Folder 0755
mach-au1x00 Folder 0755
mach-bcm47xx Folder 0755
mach-bcm63xx Folder 0755
mach-bmips Folder 0755
mach-cavium-octeon Folder 0755
mach-cobalt Folder 0755
mach-db1x00 Folder 0755
mach-dec Folder 0755
mach-generic Folder 0755
mach-ingenic Folder 0755
mach-ip22 Folder 0755
mach-ip27 Folder 0755
mach-ip28 Folder 0755
mach-ip30 Folder 0755
mach-ip32 Folder 0755
mach-jazz Folder 0755
mach-lantiq Folder 0755
mach-loongson2ef Folder 0755
mach-loongson32 Folder 0755
mach-loongson64 Folder 0755
mach-malta Folder 0755
mach-n64 Folder 0755
mach-pic32 Folder 0755
mach-ralink Folder 0755
mach-rc32434 Folder 0755
mach-rm Folder 0755
mach-sibyte Folder 0755
mach-tx49xx Folder 0755
mips-boards Folder 0755
octeon Folder 0755
pci Folder 0755
sgi Folder 0755
sibyte Folder 0755
sn Folder 0755
txx9 Folder 0755
vdso Folder 0755
xtalk Folder 0755
Kbuild File 421 B 0644
abi.h File 853 B 0644
addrspace.h File 4.02 KB 0644
amon.h File 409 B 0644
arch_hweight.h File 792 B 0644
asm-eva.h File 7.17 KB 0644
asm-offsets.h File 35 B 0644
asm-prototypes.h File 318 B 0644
asm.h File 7.16 KB 0644
asmmacro-32.h File 2.47 KB 0644
asmmacro-64.h File 1.22 KB 0644
asmmacro.h File 14.67 KB 0644
atomic.h File 7.83 KB 0644
barrier.h File 3.42 KB 0644
bcache.h File 2.04 KB 0644
bitops.h File 11.18 KB 0644
bitrev.h File 608 B 0644
bmips-spaces.h File 268 B 0644
bmips.h File 3.06 KB 0644
bootinfo.h File 4.81 KB 0644
branch.h File 2.44 KB 0644
break.h File 787 B 0644
bug.h File 759 B 0644
bugs.h File 527 B 0644
cache.h File 810 B 0644
cacheflush.h File 4.98 KB 0644
cacheops.h File 3.71 KB 0644
cachetype.h File 193 B 0644
cdmm.h File 3.68 KB 0644
cevt-r4k.h File 823 B 0644
checksum.h File 5.66 KB 0644
clocksource.h File 273 B 0644
cmp.h File 181 B 0644
cmpxchg.h File 8.69 KB 0644
compat-signal.h File 640 B 0644
compat.h File 3.45 KB 0644
compiler.h File 2.61 KB 0644
cop2.h File 1.47 KB 0644
cpu-features.h File 22.21 KB 0644
cpu-info.h File 6.16 KB 0644
cpu-type.h File 3.78 KB 0644
cpu.h File 16.31 KB 0644
cpufeature.h File 510 B 0644
debug.h File 447 B 0644
delay.h File 841 B 0644
div64.h File 2.17 KB 0644
dma-direct.h File 255 B 0644
dma-mapping.h File 349 B 0644
dma.h File 9.81 KB 0644
dmi.h File 547 B 0644
ds1287.h File 333 B 0644
dsemul.h File 3.51 KB 0644
dsp.h File 1.71 KB 0644
edac.h File 839 B 0644
elf.h File 15.19 KB 0644
elfcore-compat.h File 841 B 0644
errno.h File 429 B 0644
eva.h File 796 B 0644
exec.h File 579 B 0644
extable.h File 241 B 0644
fixmap.h File 2.17 KB 0644
floppy.h File 1.57 KB 0644
fpregdef.h File 2.1 KB 0644
fpu.h File 7.39 KB 0644
fpu_emulator.h File 4.73 KB 0644
ftrace.h File 2.7 KB 0644
futex.h File 5.43 KB 0644
ginvt.h File 1.13 KB 0644
gio_device.h File 1.38 KB 0644
gt64120.h File 18.77 KB 0644
hardirq.h File 544 B 0644
hazards.h File 8.44 KB 0644
highmem.h File 1.7 KB 0644
hpet.h File 1.93 KB 0644
hugetlb.h File 2.09 KB 0644
hw_irq.h File 475 B 0644
i8259.h File 2.38 KB 0644
idle.h File 727 B 0644
inst.h File 2.34 KB 0644
io.h File 16.26 KB 0644
irq.h File 2.2 KB 0644
irq_cpu.h File 427 B 0644
irq_gt641xx.h File 2.03 KB 0644
irq_regs.h File 540 B 0644
irqflags.h File 4.11 KB 0644
isa-rev.h File 556 B 0644
isadep.h File 573 B 0644
jazz.h File 8 KB 0644
jazzdma.h File 2.76 KB 0644
jump_label.h File 1.65 KB 0644
kdebug.h File 303 B 0644
kexec.h File 1.46 KB 0644
kgdb.h File 1.19 KB 0644
kprobes.h File 1.58 KB 0644
kvm_host.h File 29.5 KB 0644
kvm_types.h File 184 B 0644
linkage.h File 306 B 0644
local.h File 4.71 KB 0644
maar.h File 4.17 KB 0644
machine.h File 2.73 KB 0644
mc146818-time.h File 3.69 KB 0644
mc146818rtc.h File 450 B 0644
mips-cm.h File 17.11 KB 0644
mips-cpc.h File 5.63 KB 0644
mips-cps.h File 7.62 KB 0644
mips-gic.h File 12.93 KB 0644
mips-r2-to-r6-emul.h File 2.05 KB 0644
mips_mt.h File 641 B 0644
mipsmtregs.h File 12.44 KB 0644
mipsprom.h File 2.1 KB 0644
mipsregs.h File 97.75 KB 0644
mmiowb.h File 194 B 0644
mmu.h File 555 B 0644
mmu_context.h File 6.06 KB 0644
mmzone.h File 464 B 0644
module.h File 2.33 KB 0644
msa.h File 7.71 KB 0644
msc01_ic.h File 6.55 KB 0644
paccess.h File 3.07 KB 0644
page.h File 6.45 KB 0644
pci.h File 3.65 KB 0644
perf_event.h File 336 B 0644
pgalloc.h File 2.38 KB 0644
pgtable-32.h File 9.99 KB 0644
pgtable-64.h File 9.89 KB 0644
pgtable-bits.h File 7.7 KB 0644
pgtable.h File 18.57 KB 0644
pm-cps.h File 1.48 KB 0644
pm.h File 3.69 KB 0644
prefetch.h File 2.1 KB 0644
processor.h File 10.97 KB 0644
prom.h File 706 B 0644
ptrace.h File 5.55 KB 0644
r4k-timer.h File 499 B 0644
r4kcache.h File 11.2 KB 0644
reboot.h File 440 B 0644
reg.h File 26 B 0644
regdef.h File 4.95 KB 0644
rtlx.h File 2.03 KB 0644
seccomp.h File 810 B 0644
setup.h File 1.08 KB 0644
sgialib.h File 1.7 KB 0644
sgiarcs.h File 13.69 KB 0644
shmparam.h File 352 B 0644
sigcontext.h File 1.04 KB 0644
signal.h File 1.1 KB 0644
sim.h File 2.02 KB 0644
smp-cps.h File 1.22 KB 0644
smp-ops.h File 2.24 KB 0644
smp.h File 3.64 KB 0644
sni.h File 7.26 KB 0644
socket.h File 1.34 KB 0644
sparsemem.h File 486 B 0644
spinlock.h File 822 B 0644
spinlock_types.h File 188 B 0644
spram.h File 254 B 0644
stackframe.h File 10.88 KB 0644
stackprotector.h File 1022 B 0644
stacktrace.h File 2.15 KB 0644
string.h File 692 B 0644
switch_to.h File 4.35 KB 0644
sync.h File 7.64 KB 0644
syscall.h File 3.45 KB 0644
syscalls.h File 1.28 KB 0644
thread_info.h File 6.59 KB 0644
time.h File 1.58 KB 0644
timex.h File 2.87 KB 0644
tlb.h File 613 B 0644
tlbdebug.h File 403 B 0644
tlbex.h File 1014 B 0644
tlbflush.h File 1.64 KB 0644
tlbmisc.h File 320 B 0644
topology.h File 619 B 0644
traps.h File 2.39 KB 0644
txx9irq.h File 682 B 0644
txx9pio.h File 592 B 0644
txx9tmr.h File 1.52 KB 0644
types.h File 459 B 0644
uaccess.h File 14.68 KB 0644
uasm.h File 9.44 KB 0644
unaligned-emul.h File 26.23 KB 0644
unistd.h File 1.83 KB 0644
unroll.h File 2.79 KB 0644
uprobes.h File 1.11 KB 0644
vdso.h File 1.35 KB 0644
vermagic.h File 2.06 KB 0644
vga.h File 1.12 KB 0644
video.h File 875 B 0644
vmalloc.h File 90 B 0644
vpe.h File 2.53 KB 0644
watch.h File 827 B 0644
wbflush.h File 694 B 0644
yamon-dt.h File 1.68 KB 0644

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