Mr.X

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2013 Huawei Ltd.
 * Author: Jiang Liu <[email protected]>
 *
 * Copyright (C) 2014 Zi Shen Lim <[email protected]>
 */
#ifndef	__ASM_INSN_H
#define	__ASM_INSN_H
#include <linux/build_bug.h>
#include <linux/types.h>

#include <asm/insn-def.h>

#ifndef __ASSEMBLY__

enum aarch64_insn_hint_cr_op {
	AARCH64_INSN_HINT_NOP	= 0x0 << 5,
	AARCH64_INSN_HINT_YIELD	= 0x1 << 5,
	AARCH64_INSN_HINT_WFE	= 0x2 << 5,
	AARCH64_INSN_HINT_WFI	= 0x3 << 5,
	AARCH64_INSN_HINT_SEV	= 0x4 << 5,
	AARCH64_INSN_HINT_SEVL	= 0x5 << 5,

	AARCH64_INSN_HINT_XPACLRI    = 0x07 << 5,
	AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
	AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
	AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
	AARCH64_INSN_HINT_AUTIB_1716 = 0x0E << 5,
	AARCH64_INSN_HINT_PACIAZ     = 0x18 << 5,
	AARCH64_INSN_HINT_PACIASP    = 0x19 << 5,
	AARCH64_INSN_HINT_PACIBZ     = 0x1A << 5,
	AARCH64_INSN_HINT_PACIBSP    = 0x1B << 5,
	AARCH64_INSN_HINT_AUTIAZ     = 0x1C << 5,
	AARCH64_INSN_HINT_AUTIASP    = 0x1D << 5,
	AARCH64_INSN_HINT_AUTIBZ     = 0x1E << 5,
	AARCH64_INSN_HINT_AUTIBSP    = 0x1F << 5,

	AARCH64_INSN_HINT_ESB  = 0x10 << 5,
	AARCH64_INSN_HINT_PSB  = 0x11 << 5,
	AARCH64_INSN_HINT_TSB  = 0x12 << 5,
	AARCH64_INSN_HINT_CSDB = 0x14 << 5,
	AARCH64_INSN_HINT_CLEARBHB = 0x16 << 5,

	AARCH64_INSN_HINT_BTI   = 0x20 << 5,
	AARCH64_INSN_HINT_BTIC  = 0x22 << 5,
	AARCH64_INSN_HINT_BTIJ  = 0x24 << 5,
	AARCH64_INSN_HINT_BTIJC = 0x26 << 5,
};

enum aarch64_insn_imm_type {
	AARCH64_INSN_IMM_ADR,
	AARCH64_INSN_IMM_26,
	AARCH64_INSN_IMM_19,
	AARCH64_INSN_IMM_16,
	AARCH64_INSN_IMM_14,
	AARCH64_INSN_IMM_12,
	AARCH64_INSN_IMM_9,
	AARCH64_INSN_IMM_7,
	AARCH64_INSN_IMM_6,
	AARCH64_INSN_IMM_S,
	AARCH64_INSN_IMM_R,
	AARCH64_INSN_IMM_N,
	AARCH64_INSN_IMM_MAX
};

enum aarch64_insn_register_type {
	AARCH64_INSN_REGTYPE_RT,
	AARCH64_INSN_REGTYPE_RN,
	AARCH64_INSN_REGTYPE_RT2,
	AARCH64_INSN_REGTYPE_RM,
	AARCH64_INSN_REGTYPE_RD,
	AARCH64_INSN_REGTYPE_RA,
	AARCH64_INSN_REGTYPE_RS,
};

enum aarch64_insn_register {
	AARCH64_INSN_REG_0  = 0,
	AARCH64_INSN_REG_1  = 1,
	AARCH64_INSN_REG_2  = 2,
	AARCH64_INSN_REG_3  = 3,
	AARCH64_INSN_REG_4  = 4,
	AARCH64_INSN_REG_5  = 5,
	AARCH64_INSN_REG_6  = 6,
	AARCH64_INSN_REG_7  = 7,
	AARCH64_INSN_REG_8  = 8,
	AARCH64_INSN_REG_9  = 9,
	AARCH64_INSN_REG_10 = 10,
	AARCH64_INSN_REG_11 = 11,
	AARCH64_INSN_REG_12 = 12,
	AARCH64_INSN_REG_13 = 13,
	AARCH64_INSN_REG_14 = 14,
	AARCH64_INSN_REG_15 = 15,
	AARCH64_INSN_REG_16 = 16,
	AARCH64_INSN_REG_17 = 17,
	AARCH64_INSN_REG_18 = 18,
	AARCH64_INSN_REG_19 = 19,
	AARCH64_INSN_REG_20 = 20,
	AARCH64_INSN_REG_21 = 21,
	AARCH64_INSN_REG_22 = 22,
	AARCH64_INSN_REG_23 = 23,
	AARCH64_INSN_REG_24 = 24,
	AARCH64_INSN_REG_25 = 25,
	AARCH64_INSN_REG_26 = 26,
	AARCH64_INSN_REG_27 = 27,
	AARCH64_INSN_REG_28 = 28,
	AARCH64_INSN_REG_29 = 29,
	AARCH64_INSN_REG_FP = 29, /* Frame pointer */
	AARCH64_INSN_REG_30 = 30,
	AARCH64_INSN_REG_LR = 30, /* Link register */
	AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
	AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
};

enum aarch64_insn_special_register {
	AARCH64_INSN_SPCLREG_SPSR_EL1	= 0xC200,
	AARCH64_INSN_SPCLREG_ELR_EL1	= 0xC201,
	AARCH64_INSN_SPCLREG_SP_EL0	= 0xC208,
	AARCH64_INSN_SPCLREG_SPSEL	= 0xC210,
	AARCH64_INSN_SPCLREG_CURRENTEL	= 0xC212,
	AARCH64_INSN_SPCLREG_DAIF	= 0xDA11,
	AARCH64_INSN_SPCLREG_NZCV	= 0xDA10,
	AARCH64_INSN_SPCLREG_FPCR	= 0xDA20,
	AARCH64_INSN_SPCLREG_DSPSR_EL0	= 0xDA28,
	AARCH64_INSN_SPCLREG_DLR_EL0	= 0xDA29,
	AARCH64_INSN_SPCLREG_SPSR_EL2	= 0xE200,
	AARCH64_INSN_SPCLREG_ELR_EL2	= 0xE201,
	AARCH64_INSN_SPCLREG_SP_EL1	= 0xE208,
	AARCH64_INSN_SPCLREG_SPSR_INQ	= 0xE218,
	AARCH64_INSN_SPCLREG_SPSR_ABT	= 0xE219,
	AARCH64_INSN_SPCLREG_SPSR_UND	= 0xE21A,
	AARCH64_INSN_SPCLREG_SPSR_FIQ	= 0xE21B,
	AARCH64_INSN_SPCLREG_SPSR_EL3	= 0xF200,
	AARCH64_INSN_SPCLREG_ELR_EL3	= 0xF201,
	AARCH64_INSN_SPCLREG_SP_EL2	= 0xF210
};

enum aarch64_insn_system_register {
	AARCH64_INSN_SYSREG_TPIDR_EL1	= 0x4684,
	AARCH64_INSN_SYSREG_TPIDR_EL2	= 0x6682,
	AARCH64_INSN_SYSREG_SP_EL0	= 0x4208,
};

enum aarch64_insn_variant {
	AARCH64_INSN_VARIANT_32BIT,
	AARCH64_INSN_VARIANT_64BIT
};

enum aarch64_insn_condition {
	AARCH64_INSN_COND_EQ = 0x0, /* == */
	AARCH64_INSN_COND_NE = 0x1, /* != */
	AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
	AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
	AARCH64_INSN_COND_MI = 0x4, /* < 0 */
	AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
	AARCH64_INSN_COND_VS = 0x6, /* overflow */
	AARCH64_INSN_COND_VC = 0x7, /* no overflow */
	AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
	AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
	AARCH64_INSN_COND_GE = 0xa, /* signed >= */
	AARCH64_INSN_COND_LT = 0xb, /* signed < */
	AARCH64_INSN_COND_GT = 0xc, /* signed > */
	AARCH64_INSN_COND_LE = 0xd, /* signed <= */
	AARCH64_INSN_COND_AL = 0xe, /* always */
};

enum aarch64_insn_branch_type {
	AARCH64_INSN_BRANCH_NOLINK,
	AARCH64_INSN_BRANCH_LINK,
	AARCH64_INSN_BRANCH_RETURN,
	AARCH64_INSN_BRANCH_COMP_ZERO,
	AARCH64_INSN_BRANCH_COMP_NONZERO,
};

enum aarch64_insn_size_type {
	AARCH64_INSN_SIZE_8,
	AARCH64_INSN_SIZE_16,
	AARCH64_INSN_SIZE_32,
	AARCH64_INSN_SIZE_64,
};

enum aarch64_insn_ldst_type {
	AARCH64_INSN_LDST_LOAD_REG_OFFSET,
	AARCH64_INSN_LDST_STORE_REG_OFFSET,
	AARCH64_INSN_LDST_LOAD_IMM_OFFSET,
	AARCH64_INSN_LDST_STORE_IMM_OFFSET,
	AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
	AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
	AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
	AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
	AARCH64_INSN_LDST_LOAD_EX,
	AARCH64_INSN_LDST_LOAD_ACQ_EX,
	AARCH64_INSN_LDST_STORE_EX,
	AARCH64_INSN_LDST_STORE_REL_EX,
	AARCH64_INSN_LDST_SIGNED_LOAD_IMM_OFFSET,
	AARCH64_INSN_LDST_SIGNED_LOAD_REG_OFFSET,
};

enum aarch64_insn_adsb_type {
	AARCH64_INSN_ADSB_ADD,
	AARCH64_INSN_ADSB_SUB,
	AARCH64_INSN_ADSB_ADD_SETFLAGS,
	AARCH64_INSN_ADSB_SUB_SETFLAGS
};

enum aarch64_insn_movewide_type {
	AARCH64_INSN_MOVEWIDE_ZERO,
	AARCH64_INSN_MOVEWIDE_KEEP,
	AARCH64_INSN_MOVEWIDE_INVERSE
};

enum aarch64_insn_bitfield_type {
	AARCH64_INSN_BITFIELD_MOVE,
	AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
	AARCH64_INSN_BITFIELD_MOVE_SIGNED
};

enum aarch64_insn_data1_type {
	AARCH64_INSN_DATA1_REVERSE_16,
	AARCH64_INSN_DATA1_REVERSE_32,
	AARCH64_INSN_DATA1_REVERSE_64,
};

enum aarch64_insn_data2_type {
	AARCH64_INSN_DATA2_UDIV,
	AARCH64_INSN_DATA2_SDIV,
	AARCH64_INSN_DATA2_LSLV,
	AARCH64_INSN_DATA2_LSRV,
	AARCH64_INSN_DATA2_ASRV,
	AARCH64_INSN_DATA2_RORV,
};

enum aarch64_insn_data3_type {
	AARCH64_INSN_DATA3_MADD,
	AARCH64_INSN_DATA3_MSUB,
};

enum aarch64_insn_logic_type {
	AARCH64_INSN_LOGIC_AND,
	AARCH64_INSN_LOGIC_BIC,
	AARCH64_INSN_LOGIC_ORR,
	AARCH64_INSN_LOGIC_ORN,
	AARCH64_INSN_LOGIC_EOR,
	AARCH64_INSN_LOGIC_EON,
	AARCH64_INSN_LOGIC_AND_SETFLAGS,
	AARCH64_INSN_LOGIC_BIC_SETFLAGS
};

enum aarch64_insn_prfm_type {
	AARCH64_INSN_PRFM_TYPE_PLD,
	AARCH64_INSN_PRFM_TYPE_PLI,
	AARCH64_INSN_PRFM_TYPE_PST,
};

enum aarch64_insn_prfm_target {
	AARCH64_INSN_PRFM_TARGET_L1,
	AARCH64_INSN_PRFM_TARGET_L2,
	AARCH64_INSN_PRFM_TARGET_L3,
};

enum aarch64_insn_prfm_policy {
	AARCH64_INSN_PRFM_POLICY_KEEP,
	AARCH64_INSN_PRFM_POLICY_STRM,
};

enum aarch64_insn_adr_type {
	AARCH64_INSN_ADR_TYPE_ADRP,
	AARCH64_INSN_ADR_TYPE_ADR,
};

enum aarch64_insn_mem_atomic_op {
	AARCH64_INSN_MEM_ATOMIC_ADD,
	AARCH64_INSN_MEM_ATOMIC_CLR,
	AARCH64_INSN_MEM_ATOMIC_EOR,
	AARCH64_INSN_MEM_ATOMIC_SET,
	AARCH64_INSN_MEM_ATOMIC_SWP,
};

enum aarch64_insn_mem_order_type {
	AARCH64_INSN_MEM_ORDER_NONE,
	AARCH64_INSN_MEM_ORDER_ACQ,
	AARCH64_INSN_MEM_ORDER_REL,
	AARCH64_INSN_MEM_ORDER_ACQREL,
};

enum aarch64_insn_mb_type {
	AARCH64_INSN_MB_SY,
	AARCH64_INSN_MB_ST,
	AARCH64_INSN_MB_LD,
	AARCH64_INSN_MB_ISH,
	AARCH64_INSN_MB_ISHST,
	AARCH64_INSN_MB_ISHLD,
	AARCH64_INSN_MB_NSH,
	AARCH64_INSN_MB_NSHST,
	AARCH64_INSN_MB_NSHLD,
	AARCH64_INSN_MB_OSH,
	AARCH64_INSN_MB_OSHST,
	AARCH64_INSN_MB_OSHLD,
};

#define	__AARCH64_INSN_FUNCS(abbr, mask, val)				\
static __always_inline bool aarch64_insn_is_##abbr(u32 code)		\
{									\
	BUILD_BUG_ON(~(mask) & (val));					\
	return (code & (mask)) == (val);				\
}									\
static __always_inline u32 aarch64_insn_get_##abbr##_value(void)	\
{									\
	return (val);							\
}

/*
 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
 * Section C3.1 "A64 instruction index by encoding":
 * AArch64 main encoding table
 *  Bit position
 *   28 27 26 25	Encoding Group
 *   0  0  -  -		Unallocated
 *   1  0  0  -		Data processing, immediate
 *   1  0  1  -		Branch, exception generation and system instructions
 *   -  1  -  0		Loads and stores
 *   -  1  0  1		Data processing - register
 *   0  1  1  1		Data processing - SIMD and floating point
 *   1  1  1  1		Data processing - SIMD and floating point
 * "-" means "don't care"
 */
__AARCH64_INSN_FUNCS(class_branch_sys,	0x1c000000, 0x14000000)

__AARCH64_INSN_FUNCS(adr,	0x9F000000, 0x10000000)
__AARCH64_INSN_FUNCS(adrp,	0x9F000000, 0x90000000)
__AARCH64_INSN_FUNCS(prfm,	0x3FC00000, 0x39800000)
__AARCH64_INSN_FUNCS(prfm_lit,	0xFF000000, 0xD8000000)
__AARCH64_INSN_FUNCS(store_imm,	0x3FC00000, 0x39000000)
__AARCH64_INSN_FUNCS(load_imm,	0x3FC00000, 0x39400000)
__AARCH64_INSN_FUNCS(signed_load_imm, 0X3FC00000, 0x39800000)
__AARCH64_INSN_FUNCS(store_pre,	0x3FE00C00, 0x38000C00)
__AARCH64_INSN_FUNCS(load_pre,	0x3FE00C00, 0x38400C00)
__AARCH64_INSN_FUNCS(store_post,	0x3FE00C00, 0x38000400)
__AARCH64_INSN_FUNCS(load_post,	0x3FE00C00, 0x38400400)
__AARCH64_INSN_FUNCS(str_reg,	0x3FE0EC00, 0x38206800)
__AARCH64_INSN_FUNCS(str_imm,	0x3FC00000, 0x39000000)
__AARCH64_INSN_FUNCS(ldadd,	0x3F20FC00, 0x38200000)
__AARCH64_INSN_FUNCS(ldclr,	0x3F20FC00, 0x38201000)
__AARCH64_INSN_FUNCS(ldeor,	0x3F20FC00, 0x38202000)
__AARCH64_INSN_FUNCS(ldset,	0x3F20FC00, 0x38203000)
__AARCH64_INSN_FUNCS(swp,	0x3F20FC00, 0x38208000)
__AARCH64_INSN_FUNCS(cas,	0x3FA07C00, 0x08A07C00)
__AARCH64_INSN_FUNCS(ldr_reg,	0x3FE0EC00, 0x38606800)
__AARCH64_INSN_FUNCS(signed_ldr_reg, 0X3FE0FC00, 0x38A0E800)
__AARCH64_INSN_FUNCS(ldr_imm,	0x3FC00000, 0x39400000)
__AARCH64_INSN_FUNCS(ldr_lit,	0xBF000000, 0x18000000)
__AARCH64_INSN_FUNCS(ldrsw_lit,	0xFF000000, 0x98000000)
__AARCH64_INSN_FUNCS(exclusive,	0x3F800000, 0x08000000)
__AARCH64_INSN_FUNCS(load_ex,	0x3F400000, 0x08400000)
__AARCH64_INSN_FUNCS(store_ex,	0x3F400000, 0x08000000)
__AARCH64_INSN_FUNCS(mops,	0x3B200C00, 0x19000400)
__AARCH64_INSN_FUNCS(stp,	0x7FC00000, 0x29000000)
__AARCH64_INSN_FUNCS(ldp,	0x7FC00000, 0x29400000)
__AARCH64_INSN_FUNCS(stp_post,	0x7FC00000, 0x28800000)
__AARCH64_INSN_FUNCS(ldp_post,	0x7FC00000, 0x28C00000)
__AARCH64_INSN_FUNCS(stp_pre,	0x7FC00000, 0x29800000)
__AARCH64_INSN_FUNCS(ldp_pre,	0x7FC00000, 0x29C00000)
__AARCH64_INSN_FUNCS(add_imm,	0x7F000000, 0x11000000)
__AARCH64_INSN_FUNCS(adds_imm,	0x7F000000, 0x31000000)
__AARCH64_INSN_FUNCS(sub_imm,	0x7F000000, 0x51000000)
__AARCH64_INSN_FUNCS(subs_imm,	0x7F000000, 0x71000000)
__AARCH64_INSN_FUNCS(movn,	0x7F800000, 0x12800000)
__AARCH64_INSN_FUNCS(sbfm,	0x7F800000, 0x13000000)
__AARCH64_INSN_FUNCS(bfm,	0x7F800000, 0x33000000)
__AARCH64_INSN_FUNCS(movz,	0x7F800000, 0x52800000)
__AARCH64_INSN_FUNCS(ubfm,	0x7F800000, 0x53000000)
__AARCH64_INSN_FUNCS(movk,	0x7F800000, 0x72800000)
__AARCH64_INSN_FUNCS(add,	0x7F200000, 0x0B000000)
__AARCH64_INSN_FUNCS(adds,	0x7F200000, 0x2B000000)
__AARCH64_INSN_FUNCS(sub,	0x7F200000, 0x4B000000)
__AARCH64_INSN_FUNCS(subs,	0x7F200000, 0x6B000000)
__AARCH64_INSN_FUNCS(madd,	0x7FE08000, 0x1B000000)
__AARCH64_INSN_FUNCS(msub,	0x7FE08000, 0x1B008000)
__AARCH64_INSN_FUNCS(udiv,	0x7FE0FC00, 0x1AC00800)
__AARCH64_INSN_FUNCS(sdiv,	0x7FE0FC00, 0x1AC00C00)
__AARCH64_INSN_FUNCS(lslv,	0x7FE0FC00, 0x1AC02000)
__AARCH64_INSN_FUNCS(lsrv,	0x7FE0FC00, 0x1AC02400)
__AARCH64_INSN_FUNCS(asrv,	0x7FE0FC00, 0x1AC02800)
__AARCH64_INSN_FUNCS(rorv,	0x7FE0FC00, 0x1AC02C00)
__AARCH64_INSN_FUNCS(rev16,	0x7FFFFC00, 0x5AC00400)
__AARCH64_INSN_FUNCS(rev32,	0x7FFFFC00, 0x5AC00800)
__AARCH64_INSN_FUNCS(rev64,	0x7FFFFC00, 0x5AC00C00)
__AARCH64_INSN_FUNCS(and,	0x7F200000, 0x0A000000)
__AARCH64_INSN_FUNCS(bic,	0x7F200000, 0x0A200000)
__AARCH64_INSN_FUNCS(orr,	0x7F200000, 0x2A000000)
__AARCH64_INSN_FUNCS(mov_reg,	0x7FE0FFE0, 0x2A0003E0)
__AARCH64_INSN_FUNCS(orn,	0x7F200000, 0x2A200000)
__AARCH64_INSN_FUNCS(eor,	0x7F200000, 0x4A000000)
__AARCH64_INSN_FUNCS(eon,	0x7F200000, 0x4A200000)
__AARCH64_INSN_FUNCS(ands,	0x7F200000, 0x6A000000)
__AARCH64_INSN_FUNCS(bics,	0x7F200000, 0x6A200000)
__AARCH64_INSN_FUNCS(and_imm,	0x7F800000, 0x12000000)
__AARCH64_INSN_FUNCS(orr_imm,	0x7F800000, 0x32000000)
__AARCH64_INSN_FUNCS(eor_imm,	0x7F800000, 0x52000000)
__AARCH64_INSN_FUNCS(ands_imm,	0x7F800000, 0x72000000)
__AARCH64_INSN_FUNCS(extr,	0x7FA00000, 0x13800000)
__AARCH64_INSN_FUNCS(b,		0xFC000000, 0x14000000)
__AARCH64_INSN_FUNCS(bl,	0xFC000000, 0x94000000)
__AARCH64_INSN_FUNCS(cbz,	0x7F000000, 0x34000000)
__AARCH64_INSN_FUNCS(cbnz,	0x7F000000, 0x35000000)
__AARCH64_INSN_FUNCS(tbz,	0x7F000000, 0x36000000)
__AARCH64_INSN_FUNCS(tbnz,	0x7F000000, 0x37000000)
__AARCH64_INSN_FUNCS(bcond,	0xFF000010, 0x54000000)
__AARCH64_INSN_FUNCS(svc,	0xFFE0001F, 0xD4000001)
__AARCH64_INSN_FUNCS(hvc,	0xFFE0001F, 0xD4000002)
__AARCH64_INSN_FUNCS(smc,	0xFFE0001F, 0xD4000003)
__AARCH64_INSN_FUNCS(brk,	0xFFE0001F, 0xD4200000)
__AARCH64_INSN_FUNCS(exception,	0xFF000000, 0xD4000000)
__AARCH64_INSN_FUNCS(hint,	0xFFFFF01F, 0xD503201F)
__AARCH64_INSN_FUNCS(br,	0xFFFFFC1F, 0xD61F0000)
__AARCH64_INSN_FUNCS(br_auth,	0xFEFFF800, 0xD61F0800)
__AARCH64_INSN_FUNCS(blr,	0xFFFFFC1F, 0xD63F0000)
__AARCH64_INSN_FUNCS(blr_auth,	0xFEFFF800, 0xD63F0800)
__AARCH64_INSN_FUNCS(ret,	0xFFFFFC1F, 0xD65F0000)
__AARCH64_INSN_FUNCS(ret_auth,	0xFFFFFBFF, 0xD65F0BFF)
__AARCH64_INSN_FUNCS(eret,	0xFFFFFFFF, 0xD69F03E0)
__AARCH64_INSN_FUNCS(eret_auth,	0xFFFFFBFF, 0xD69F0BFF)
__AARCH64_INSN_FUNCS(mrs,	0xFFF00000, 0xD5300000)
__AARCH64_INSN_FUNCS(msr_imm,	0xFFF8F01F, 0xD500401F)
__AARCH64_INSN_FUNCS(msr_reg,	0xFFF00000, 0xD5100000)
__AARCH64_INSN_FUNCS(dmb,	0xFFFFF0FF, 0xD50330BF)
__AARCH64_INSN_FUNCS(dsb_base,	0xFFFFF0FF, 0xD503309F)
__AARCH64_INSN_FUNCS(dsb_nxs,	0xFFFFF3FF, 0xD503323F)
__AARCH64_INSN_FUNCS(isb,	0xFFFFF0FF, 0xD50330DF)
__AARCH64_INSN_FUNCS(sb,	0xFFFFFFFF, 0xD50330FF)
__AARCH64_INSN_FUNCS(clrex,	0xFFFFF0FF, 0xD503305F)
__AARCH64_INSN_FUNCS(ssbb,	0xFFFFFFFF, 0xD503309F)
__AARCH64_INSN_FUNCS(pssbb,	0xFFFFFFFF, 0xD503349F)
__AARCH64_INSN_FUNCS(bti,	0xFFFFFF3F, 0xD503241f)

#undef	__AARCH64_INSN_FUNCS

static __always_inline bool aarch64_insn_is_steppable_hint(u32 insn)
{
	if (!aarch64_insn_is_hint(insn))
		return false;

	switch (insn & 0xFE0) {
	case AARCH64_INSN_HINT_XPACLRI:
	case AARCH64_INSN_HINT_PACIA_1716:
	case AARCH64_INSN_HINT_PACIB_1716:
	case AARCH64_INSN_HINT_PACIAZ:
	case AARCH64_INSN_HINT_PACIASP:
	case AARCH64_INSN_HINT_PACIBZ:
	case AARCH64_INSN_HINT_PACIBSP:
	case AARCH64_INSN_HINT_BTI:
	case AARCH64_INSN_HINT_BTIC:
	case AARCH64_INSN_HINT_BTIJ:
	case AARCH64_INSN_HINT_BTIJC:
	case AARCH64_INSN_HINT_NOP:
		return true;
	default:
		return false;
	}
}

static __always_inline bool aarch64_insn_is_branch(u32 insn)
{
	/* b, bl, cb*, tb*, ret*, b.cond, br*, blr* */

	return aarch64_insn_is_b(insn) ||
	       aarch64_insn_is_bl(insn) ||
	       aarch64_insn_is_cbz(insn) ||
	       aarch64_insn_is_cbnz(insn) ||
	       aarch64_insn_is_tbz(insn) ||
	       aarch64_insn_is_tbnz(insn) ||
	       aarch64_insn_is_ret(insn) ||
	       aarch64_insn_is_ret_auth(insn) ||
	       aarch64_insn_is_br(insn) ||
	       aarch64_insn_is_br_auth(insn) ||
	       aarch64_insn_is_blr(insn) ||
	       aarch64_insn_is_blr_auth(insn) ||
	       aarch64_insn_is_bcond(insn);
}

static __always_inline bool aarch64_insn_is_branch_imm(u32 insn)
{
	return aarch64_insn_is_b(insn) ||
	       aarch64_insn_is_bl(insn) ||
	       aarch64_insn_is_tbz(insn) ||
	       aarch64_insn_is_tbnz(insn) ||
	       aarch64_insn_is_cbz(insn) ||
	       aarch64_insn_is_cbnz(insn) ||
	       aarch64_insn_is_bcond(insn);
}

static __always_inline bool aarch64_insn_is_adr_adrp(u32 insn)
{
	return aarch64_insn_is_adr(insn) ||
	       aarch64_insn_is_adrp(insn);
}

static __always_inline bool aarch64_insn_is_dsb(u32 insn)
{
	return aarch64_insn_is_dsb_base(insn) ||
	       aarch64_insn_is_dsb_nxs(insn);
}

static __always_inline bool aarch64_insn_is_barrier(u32 insn)
{
	return aarch64_insn_is_dmb(insn) ||
	       aarch64_insn_is_dsb(insn) ||
	       aarch64_insn_is_isb(insn) ||
	       aarch64_insn_is_sb(insn) ||
	       aarch64_insn_is_clrex(insn) ||
	       aarch64_insn_is_ssbb(insn) ||
	       aarch64_insn_is_pssbb(insn);
}

static __always_inline bool aarch64_insn_is_store_single(u32 insn)
{
	return aarch64_insn_is_store_imm(insn) ||
	       aarch64_insn_is_store_pre(insn) ||
	       aarch64_insn_is_store_post(insn);
}

static __always_inline bool aarch64_insn_is_store_pair(u32 insn)
{
	return aarch64_insn_is_stp(insn) ||
	       aarch64_insn_is_stp_pre(insn) ||
	       aarch64_insn_is_stp_post(insn);
}

static __always_inline bool aarch64_insn_is_load_single(u32 insn)
{
	return aarch64_insn_is_load_imm(insn) ||
	       aarch64_insn_is_load_pre(insn) ||
	       aarch64_insn_is_load_post(insn);
}

static __always_inline bool aarch64_insn_is_load_pair(u32 insn)
{
	return aarch64_insn_is_ldp(insn) ||
	       aarch64_insn_is_ldp_pre(insn) ||
	       aarch64_insn_is_ldp_post(insn);
}

static __always_inline bool aarch64_insn_uses_literal(u32 insn)
{
	/* ldr/ldrsw (literal), prfm */

	return aarch64_insn_is_ldr_lit(insn) ||
	       aarch64_insn_is_ldrsw_lit(insn) ||
	       aarch64_insn_is_adr_adrp(insn) ||
	       aarch64_insn_is_prfm_lit(insn);
}

enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
				  u32 insn, u64 imm);
u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
					 u32 insn);
u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
				enum aarch64_insn_branch_type type);
u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
				     enum aarch64_insn_register reg,
				     enum aarch64_insn_variant variant,
				     enum aarch64_insn_branch_type type);
u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
				     enum aarch64_insn_condition cond);

static __always_inline u32
aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op)
{
	return aarch64_insn_get_hint_value() | op;
}

static __always_inline u32 aarch64_insn_gen_nop(void)
{
	return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
}

static __always_inline bool aarch64_insn_is_nop(u32 insn)
{
	return insn == aarch64_insn_gen_nop();
}

u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
				enum aarch64_insn_branch_type type);
u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
				    enum aarch64_insn_register base,
				    enum aarch64_insn_register offset,
				    enum aarch64_insn_size_type size,
				    enum aarch64_insn_ldst_type type);
u32 aarch64_insn_gen_load_store_imm(enum aarch64_insn_register reg,
				    enum aarch64_insn_register base,
				    unsigned int imm,
				    enum aarch64_insn_size_type size,
				    enum aarch64_insn_ldst_type type);
u32 aarch64_insn_gen_load_literal(unsigned long pc, unsigned long addr,
				  enum aarch64_insn_register reg,
				  bool is64bit);
u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
				     enum aarch64_insn_register reg2,
				     enum aarch64_insn_register base,
				     int offset,
				     enum aarch64_insn_variant variant,
				     enum aarch64_insn_ldst_type type);
u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
				   enum aarch64_insn_register base,
				   enum aarch64_insn_register state,
				   enum aarch64_insn_size_type size,
				   enum aarch64_insn_ldst_type type);
u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
				 enum aarch64_insn_register src,
				 int imm, enum aarch64_insn_variant variant,
				 enum aarch64_insn_adsb_type type);
u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
			 enum aarch64_insn_register reg,
			 enum aarch64_insn_adr_type type);
u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
			      enum aarch64_insn_register src,
			      int immr, int imms,
			      enum aarch64_insn_variant variant,
			      enum aarch64_insn_bitfield_type type);
u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
			      int imm, int shift,
			      enum aarch64_insn_variant variant,
			      enum aarch64_insn_movewide_type type);
u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
					 enum aarch64_insn_register src,
					 enum aarch64_insn_register reg,
					 int shift,
					 enum aarch64_insn_variant variant,
					 enum aarch64_insn_adsb_type type);
u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
			   enum aarch64_insn_register src,
			   enum aarch64_insn_variant variant,
			   enum aarch64_insn_data1_type type);
u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
			   enum aarch64_insn_register src,
			   enum aarch64_insn_register reg,
			   enum aarch64_insn_variant variant,
			   enum aarch64_insn_data2_type type);
u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
			   enum aarch64_insn_register src,
			   enum aarch64_insn_register reg1,
			   enum aarch64_insn_register reg2,
			   enum aarch64_insn_variant variant,
			   enum aarch64_insn_data3_type type);
u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
					 enum aarch64_insn_register src,
					 enum aarch64_insn_register reg,
					 int shift,
					 enum aarch64_insn_variant variant,
					 enum aarch64_insn_logic_type type);
u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,
			      enum aarch64_insn_register src,
			      enum aarch64_insn_variant variant);
u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
				       enum aarch64_insn_variant variant,
				       enum aarch64_insn_register Rn,
				       enum aarch64_insn_register Rd,
				       u64 imm);
u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
			  enum aarch64_insn_register Rm,
			  enum aarch64_insn_register Rn,
			  enum aarch64_insn_register Rd,
			  u8 lsb);
#ifdef CONFIG_ARM64_LSE_ATOMICS
u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
				  enum aarch64_insn_register address,
				  enum aarch64_insn_register value,
				  enum aarch64_insn_size_type size,
				  enum aarch64_insn_mem_atomic_op op,
				  enum aarch64_insn_mem_order_type order);
u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
			 enum aarch64_insn_register address,
			 enum aarch64_insn_register value,
			 enum aarch64_insn_size_type size,
			 enum aarch64_insn_mem_order_type order);
#else
static inline
u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
				  enum aarch64_insn_register address,
				  enum aarch64_insn_register value,
				  enum aarch64_insn_size_type size,
				  enum aarch64_insn_mem_atomic_op op,
				  enum aarch64_insn_mem_order_type order)
{
	return AARCH64_BREAK_FAULT;
}

static inline
u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
			 enum aarch64_insn_register address,
			 enum aarch64_insn_register value,
			 enum aarch64_insn_size_type size,
			 enum aarch64_insn_mem_order_type order)
{
	return AARCH64_BREAK_FAULT;
}
#endif
u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type);
u32 aarch64_insn_gen_dsb(enum aarch64_insn_mb_type type);
u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
			 enum aarch64_insn_system_register sysreg);

s32 aarch64_get_branch_offset(u32 insn);
u32 aarch64_set_branch_offset(u32 insn, s32 offset);

s32 aarch64_insn_adrp_get_offset(u32 insn);
u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);

bool aarch32_insn_is_wide(u32 insn);

#define A32_RN_OFFSET	16
#define A32_RT_OFFSET	12
#define A32_RT2_OFFSET	 0

u32 aarch64_insn_extract_system_reg(u32 insn);
u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
u32 aarch32_insn_mcr_extract_opc2(u32 insn);
u32 aarch32_insn_mcr_extract_crm(u32 insn);

typedef bool (pstate_check_t)(unsigned long);
extern pstate_check_t * const aarch32_opcode_cond_checks[16];

#endif /* __ASSEMBLY__ */

#endif	/* __ASM_INSN_H */

Name	Type	Size	Permission
stacktrace	Folder		0755
vdso	Folder		0755
xen	Folder		0755
Kbuild	File	528 B	0644
acenv.h	File	395 B	0644
acpi.h	File	5.48 KB	0644
alternative-macros.h	File	6.45 KB	0644
alternative.h	File	1.08 KB	0644
apple_m1_pmu.h	File	2.23 KB	0644
arch_gicv3.h	File	4.44 KB	0644
arch_timer.h	File	4.84 KB	0644
archrandom.h	File	2.99 KB	0644
arm-cci.h	File	254 B	0644
arm_dsu_pmu.h	File	2.94 KB	0644
arm_pmuv3.h	File	3.4 KB	0644
asm-bug.h	File	952 B	0644
asm-extable.h	File	3.59 KB	0644
asm-offsets.h	File	35 B	0644
asm-prototypes.h	File	958 B	0644
asm-uaccess.h	File	2.38 KB	0644
asm_pointer_auth.h	File	2.49 KB	0644
assembler.h	File	21.19 KB	0644
atomic.h	File	7.23 KB	0644
atomic_ll_sc.h	File	10.75 KB	0644
atomic_lse.h	File	8.2 KB	0644
barrier.h	File	5.85 KB	0644
bitops.h	File	813 B	0644
bitrev.h	File	452 B	0644
boot.h	File	369 B	0644
brk-imm.h	File	1.27 KB	0644
bug.h	File	572 B	0644
cache.h	File	3.28 KB	0644
cacheflush.h	File	4.61 KB	0644
checksum.h	File	1.06 KB	0644
clocksource.h	File	136 B	0644
cmpxchg.h	File	7.15 KB	0644
compat.h	File	2.13 KB	0644
compiler.h	File	979 B	0644
cpu.h	File	1.57 KB	0644
cpu_ops.h	File	1.92 KB	0644
cpucaps.h	File	2.28 KB	0644
cpufeature.h	File	32.74 KB	0644
cpuidle.h	File	1.03 KB	0644
cputype.h	File	13.99 KB	0644
crash_reserve.h	File	335 B	0644
current.h	File	517 B	0644
daifflags.h	File	3.45 KB	0644
dcc.h	File	981 B	0644
debug-monitors.h	File	3.26 KB	0644
device.h	File	189 B	0644
dmi.h	File	850 B	0644
efi.h	File	5.05 KB	0644
el2_setup.h	File	11.6 KB	0644
elf.h	File	8 KB	0644
esr.h	File	17.16 KB	0644
exception.h	File	3.29 KB	0644
exec.h	File	278 B	0644
extable.h	File	1.36 KB	0644
fixmap.h	File	3.11 KB	0644
fpsimd.h	File	11.63 KB	0644
fpsimdmacros.h	File	7.7 KB	0644
fpu.h	File	309 B	0644
ftrace.h	File	5.93 KB	0644
futex.h	File	2.71 KB	0644
gcs.h	File	2.1 KB	0644
gpr-num.h	File	708 B	0644
hardirq.h	File	2.28 KB	0644
hugetlb.h	File	3.07 KB	0644
hw_breakpoint.h	File	4.16 KB	0644
hwcap.h	File	8.77 KB	0644
hyp_image.h	File	1.87 KB	0644
hypervisor.h	File	444 B	0644
image.h	File	1.48 KB	0644
insn-def.h	File	571 B	0644
insn.h	File	23.8 KB	0644
io.h	File	8.9 KB	0644
irq.h	File	571 B	0644
irq_work.h	File	192 B	0644
irqflags.h	File	4.31 KB	0644
jump_label.h	File	1.32 KB	0644
kasan.h	File	578 B	0644
kernel-pgtable.h	File	3.3 KB	0644
kexec.h	File	3.37 KB	0644
kfence.h	File	680 B	0644
kgdb.h	File	3.27 KB	0644
kprobes.h	File	965 B	0644
kvm_arm.h	File	14.34 KB	0644
kvm_asm.h	File	12.18 KB	0644
kvm_emulate.h	File	16.59 KB	0644
kvm_host.h	File	47.41 KB	0644
kvm_hyp.h	File	5.14 KB	0644
kvm_mmu.h	File	11.14 KB	0644
kvm_mte.h	File	1.35 KB	0644
kvm_nested.h	File	6.23 KB	0644
kvm_pgtable.h	File	28.64 KB	0644
kvm_pkvm.h	File	5.35 KB	0644
kvm_ptrauth.h	File	4.04 KB	0644
kvm_ras.h	File	594 B	0644
kvm_types.h	File	185 B	0644
linkage.h	File	1.19 KB	0644
lse.h	File	933 B	0644
mem_encrypt.h	File	999 B	0644
memory.h	File	14.24 KB	0644
mman.h	File	2.36 KB	0644
mmu.h	File	3.47 KB	0644
mmu_context.h	File	8.5 KB	0644
module.h	File	1.73 KB	0644
module.lds.h	File	795 B	0644
mshyperv.h	File	1.34 KB	0644
mte-def.h	File	577 B	0644
mte-kasan.h	File	5.58 KB	0644
mte.h	File	6.99 KB	0644
neon-intrinsics.h	File	959 B	0644
neon.h	File	385 B	0644
numa.h	File	165 B	0644
page-def.h	File	296 B	0644
page.h	File	1.34 KB	0644
paravirt.h	File	580 B	0644
paravirt_api_clock.h	File	26 B	0644
pci.h	File	469 B	0644
percpu.h	File	8.31 KB	0644
perf_event.h	File	515 B	0644
pgalloc.h	File	3.04 KB	0644
pgtable-hwdef.h	File	11.47 KB	0644
pgtable-prot.h	File	8.19 KB	0644
pgtable-types.h	File	1.41 KB	0644
pgtable.h	File	52.72 KB	0644
pkeys.h	File	2.36 KB	0644
pointer_auth.h	File	4.68 KB	0644
por.h	File	635 B	0644
preempt.h	File	2.71 KB	0644
probes.h	File	549 B	0644
proc-fns.h	File	562 B	0644
processor.h	File	12.19 KB	0644
ptdump.h	File	1.78 KB	0644
ptrace.h	File	9.35 KB	0644
pvclock-abi.h	File	374 B	0644
rsi.h	File	1.64 KB	0644
rsi_cmds.h	File	3.85 KB	0644
rsi_smc.h	File	5.23 KB	0644
runtime-const.h	File	2.3 KB	0644
rwonce.h	File	1.96 KB	0644
scs.h	File	1.09 KB	0644
sdei.h	File	1.53 KB	0644
seccomp.h	File	891 B	0644
sections.h	File	1.14 KB	0644
semihost.h	File	537 B	0644
set_memory.h	File	715 B	0644
setup.h	File	789 B	0644
shmparam.h	File	425 B	0644
signal.h	File	650 B	0644
signal32.h	File	1.93 KB	0644
simd.h	File	1.04 KB	0644
smp.h	File	3.44 KB	0644
smp_plat.h	File	824 B	0644
sparsemem.h	File	747 B	0644
spectre.h	File	3.75 KB	0644
spinlock.h	File	601 B	0644
spinlock_types.h	File	366 B	0644
stack_pointer.h	File	247 B	0644
stackprotector.h	File	1.15 KB	0644
stacktrace.h	File	2.96 KB	0644
stage2_pgtable.h	File	1.03 KB	0644
stat.h	File	947 B	0644
string.h	File	1.89 KB	0644
suspend.h	File	1.65 KB	0644
sync_bitops.h	File	1.06 KB	0644
syscall.h	File	1.97 KB	0644
syscall_wrapper.h	File	3.09 KB	0644
sysreg.h	File	46.33 KB	0644
system_misc.h	File	880 B	0644
text-patching.h	File	544 B	0644
thread_info.h	File	3.96 KB	0644
timex.h	File	343 B	0644
tlb.h	File	2.65 KB	0644
tlbbatch.h	File	281 B	0644
tlbflush.h	File	17.05 KB	0644
topology.h	File	1.22 KB	0644
trans_pgd.h	File	1.02 KB	0644
traps.h	File	4.37 KB	0644
uaccess.h	File	14.43 KB	0644
unistd.h	File	898 B	0644
unistd32.h	File	240 B	0644
uprobes.h	File	579 B	0644
vdso.h	File	468 B	0644
vectors.h	File	1.74 KB	0644
vermagic.h	File	200 B	0644
virt.h	File	4.26 KB	0644
vmalloc.h	File	805 B	0644
vmap_stack.h	File	739 B	0644
vncr_mapping.h	File	3.56 KB	0644
word-at-a-time.h	File	1.5 KB	0644
xor.h	File	1.88 KB	0644

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