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/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2013 - ARM Ltd * Author: Marc Zyngier <[email protected]> */ #ifndef __ASM_ESR_H #define __ASM_ESR_H #include <asm/memory.h> #include <asm/sysreg.h> #define ESR_ELx_EC_UNKNOWN UL(0x00) #define ESR_ELx_EC_WFx UL(0x01) /* Unallocated EC: 0x02 */ #define ESR_ELx_EC_CP15_32 UL(0x03) #define ESR_ELx_EC_CP15_64 UL(0x04) #define ESR_ELx_EC_CP14_MR UL(0x05) #define ESR_ELx_EC_CP14_LS UL(0x06) #define ESR_ELx_EC_FP_ASIMD UL(0x07) #define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */ #define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */ /* Unallocated EC: 0x0A - 0x0B */ #define ESR_ELx_EC_CP14_64 UL(0x0C) #define ESR_ELx_EC_BTI UL(0x0D) #define ESR_ELx_EC_ILL UL(0x0E) /* Unallocated EC: 0x0F - 0x10 */ #define ESR_ELx_EC_SVC32 UL(0x11) #define ESR_ELx_EC_HVC32 UL(0x12) /* EL2 only */ #define ESR_ELx_EC_SMC32 UL(0x13) /* EL2 and above */ /* Unallocated EC: 0x14 */ #define ESR_ELx_EC_SVC64 UL(0x15) #define ESR_ELx_EC_HVC64 UL(0x16) /* EL2 and above */ #define ESR_ELx_EC_SMC64 UL(0x17) /* EL2 and above */ #define ESR_ELx_EC_SYS64 UL(0x18) #define ESR_ELx_EC_SVE UL(0x19) #define ESR_ELx_EC_ERET UL(0x1a) /* EL2 only */ /* Unallocated EC: 0x1B */ #define ESR_ELx_EC_FPAC UL(0x1C) /* EL1 and above */ #define ESR_ELx_EC_SME UL(0x1D) /* Unallocated EC: 0x1E */ #define ESR_ELx_EC_IMP_DEF UL(0x1f) /* EL3 only */ #define ESR_ELx_EC_IABT_LOW UL(0x20) #define ESR_ELx_EC_IABT_CUR UL(0x21) #define ESR_ELx_EC_PC_ALIGN UL(0x22) /* Unallocated EC: 0x23 */ #define ESR_ELx_EC_DABT_LOW UL(0x24) #define ESR_ELx_EC_DABT_CUR UL(0x25) #define ESR_ELx_EC_SP_ALIGN UL(0x26) #define ESR_ELx_EC_MOPS UL(0x27) #define ESR_ELx_EC_FP_EXC32 UL(0x28) /* Unallocated EC: 0x29 - 0x2B */ #define ESR_ELx_EC_FP_EXC64 UL(0x2C) #define ESR_ELx_EC_GCS UL(0x2D) /* Unallocated EC: 0x2E */ #define ESR_ELx_EC_SERROR UL(0x2F) #define ESR_ELx_EC_BREAKPT_LOW UL(0x30) #define ESR_ELx_EC_BREAKPT_CUR UL(0x31) #define ESR_ELx_EC_SOFTSTP_LOW UL(0x32) #define ESR_ELx_EC_SOFTSTP_CUR UL(0x33) #define ESR_ELx_EC_WATCHPT_LOW UL(0x34) #define ESR_ELx_EC_WATCHPT_CUR UL(0x35) /* Unallocated EC: 0x36 - 0x37 */ #define ESR_ELx_EC_BKPT32 UL(0x38) /* Unallocated EC: 0x39 */ #define ESR_ELx_EC_VECTOR32 UL(0x3A) /* EL2 only */ /* Unallocated EC: 0x3B */ #define ESR_ELx_EC_BRK64 UL(0x3C) /* Unallocated EC: 0x3D - 0x3F */ #define ESR_ELx_EC_MAX UL(0x3F) #define ESR_ELx_EC_SHIFT (26) #define ESR_ELx_EC_WIDTH (6) #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) #define ESR_ELx_IL_SHIFT (25) #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) #define ESR_ELx_ISS_MASK (GENMASK(24, 0)) #define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK) #define ESR_ELx_ISS2_SHIFT (32) #define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32)) #define ESR_ELx_ISS2(esr) (((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT) /* ISS field definitions shared by different classes */ #define ESR_ELx_WNR_SHIFT (6) #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) /* Asynchronous Error Type */ #define ESR_ELx_IDS_SHIFT (24) #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT) #define ESR_ELx_AET_SHIFT (10) #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT) #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT) #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT) #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT) #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT) #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) /* Shared ISS field definitions for Data/Instruction aborts */ #define ESR_ELx_SET_SHIFT (11) #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) #define ESR_ELx_FnV_SHIFT (10) #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) #define ESR_ELx_EA_SHIFT (9) #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) #define ESR_ELx_S1PTW_SHIFT (7) #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ #define ESR_ELx_FSC (0x3F) #define ESR_ELx_FSC_TYPE (0x3C) #define ESR_ELx_FSC_LEVEL (0x03) #define ESR_ELx_FSC_EXTABT (0x10) #define ESR_ELx_FSC_MTE (0x11) #define ESR_ELx_FSC_SERROR (0x11) #define ESR_ELx_FSC_ACCESS (0x08) #define ESR_ELx_FSC_FAULT (0x04) #define ESR_ELx_FSC_PERM (0x0C) #define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n)) #define ESR_ELx_FSC_SECC (0x18) #define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n)) /* Status codes for individual page table levels */ #define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + (n)) #define ESR_ELx_FSC_PERM_L(n) (ESR_ELx_FSC_PERM + (n)) #define ESR_ELx_FSC_FAULT_nL (0x2C) #define ESR_ELx_FSC_FAULT_L(n) (((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \ ESR_ELx_FSC_FAULT) + (n)) /* ISS field definitions for Data Aborts */ #define ESR_ELx_ISV_SHIFT (24) #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) #define ESR_ELx_SAS_SHIFT (22) #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) #define ESR_ELx_SSE_SHIFT (21) #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) #define ESR_ELx_SRT_SHIFT (16) #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) #define ESR_ELx_SF_SHIFT (15) #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) #define ESR_ELx_AR_SHIFT (14) #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) #define ESR_ELx_CM_SHIFT (8) #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) /* ISS2 field definitions for Data Aborts */ #define ESR_ELx_TnD_SHIFT (10) #define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT) #define ESR_ELx_TagAccess_SHIFT (9) #define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT) #define ESR_ELx_GCS_SHIFT (8) #define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT) #define ESR_ELx_Overlay_SHIFT (6) #define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT) #define ESR_ELx_DirtyBit_SHIFT (5) #define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT) #define ESR_ELx_Xs_SHIFT (0) #define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0)) /* ISS field definitions for exceptions taken in to Hyp */ #define ESR_ELx_FSC_ADDRSZ (0x00) #define ESR_ELx_FSC_ADDRSZ_L(n) (ESR_ELx_FSC_ADDRSZ + (n)) #define ESR_ELx_CV (UL(1) << 24) #define ESR_ELx_COND_SHIFT (20) #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5) #define ESR_ELx_WFx_ISS_RV (UL(1) << 2) #define ESR_ELx_WFx_ISS_TI (UL(3) << 0) #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0) #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) #define DISR_EL1_IDS (UL(1) << 24) /* * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean * different things in the future... */ #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) /* ESR value templates for specific events */ #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \ (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT)) #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ ESR_ELx_WFx_ISS_WFI) /* BRK instruction trap from AArch64 state */ #define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff /* ISS field definitions for System instruction traps */ #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ ESR_ELx_SYS64_ISS_OP1_MASK | \ ESR_ELx_SYS64_ISS_OP2_MASK | \ ESR_ELx_SYS64_ISS_CRN_MASK | \ ESR_ELx_SYS64_ISS_CRM_MASK) #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ ESR_ELx_SYS64_ISS_DIR_MASK) #define ESR_ELx_SYS64_ISS_RT(esr) \ (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT) /* * User space cache operations have the following sysreg encoding * in System instructions. * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) */ #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ ESR_ELx_SYS64_ISS_OP1_MASK | \ ESR_ELx_SYS64_ISS_OP2_MASK | \ ESR_ELx_SYS64_ISS_CRN_MASK | \ ESR_ELx_SYS64_ISS_DIR_MASK) #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ ESR_ELx_SYS64_ISS_DIR_WRITE) /* * User space MRS operations which are supported for emulation * have the following sysreg encoding in System instructions. * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1) */ #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ ESR_ELx_SYS64_ISS_OP1_MASK | \ ESR_ELx_SYS64_ISS_CRN_MASK | \ ESR_ELx_SYS64_ISS_DIR_MASK) #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \ ESR_ELx_SYS64_ISS_DIR_READ) #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ ESR_ELx_SYS64_ISS_DIR_READ) #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ ESR_ELx_SYS64_ISS_DIR_READ) #define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \ ESR_ELx_SYS64_ISS_DIR_READ) #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ ESR_ELx_SYS64_ISS_DIR_READ) #define esr_sys64_to_sysreg(e) \ sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ ESR_ELx_SYS64_ISS_OP0_SHIFT), \ (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ ESR_ELx_SYS64_ISS_OP1_SHIFT), \ (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ ESR_ELx_SYS64_ISS_CRN_SHIFT), \ (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ ESR_ELx_SYS64_ISS_CRM_SHIFT), \ (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ ESR_ELx_SYS64_ISS_OP2_SHIFT)) #define esr_cp15_to_sysreg(e) \ sys_reg(3, \ (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ ESR_ELx_SYS64_ISS_OP1_SHIFT), \ (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ ESR_ELx_SYS64_ISS_CRN_SHIFT), \ (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ ESR_ELx_SYS64_ISS_CRM_SHIFT), \ (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ ESR_ELx_SYS64_ISS_OP2_SHIFT)) /* ISS field definitions for ERET/ERETAA/ERETAB trapping */ #define ESR_ELx_ERET_ISS_ERET 0x2 #define ESR_ELx_ERET_ISS_ERETA 0x1 /* * ISS field definitions for floating-point exception traps * (FP_EXC_32/FP_EXC_64). * * (The FPEXC_* constants are used instead for common bits.) */ #define ESR_ELx_FP_EXC_TFV (UL(1) << 23) /* * ISS field definitions for CP15 accesses */ #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1 #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1 #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0 #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT) #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT) #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \ ESR_ELx_CP15_32_ISS_OP2_MASK | \ ESR_ELx_CP15_32_ISS_CRN_MASK | \ ESR_ELx_CP15_32_ISS_CRM_MASK | \ ESR_ELx_CP15_32_ISS_DIR_MASK) #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \ ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \ ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \ ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)) #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1 #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1 #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0 #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT) #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT) #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT) #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \ ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)) #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \ ESR_ELx_CP15_64_ISS_CRM_MASK | \ ESR_ELx_CP15_64_ISS_DIR_MASK) #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \ ESR_ELx_CP15_64_ISS_DIR_READ) #define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \ ESR_ELx_CP15_64_ISS_DIR_READ) #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\ ESR_ELx_CP15_32_ISS_DIR_READ) /* * ISS values for SME traps */ #define ESR_ELx_SME_ISS_SMTC_MASK GENMASK(2, 0) #define ESR_ELx_SME_ISS_SMTC(esr) ((esr) & ESR_ELx_SME_ISS_SMTC_MASK) #define ESR_ELx_SME_ISS_SMTC_SME_DISABLED 0 #define ESR_ELx_SME_ISS_SMTC_ILL 1 #define ESR_ELx_SME_ISS_SMTC_SM_DISABLED 2 #define ESR_ELx_SME_ISS_SMTC_ZA_DISABLED 3 #define ESR_ELx_SME_ISS_SMTC_ZT_DISABLED 4 /* ISS field definitions for MOPS exceptions */ #define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24) #define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18) #define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17) #define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16) #define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10) #define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5) #define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0) /* ISS field definitions for GCS */ #define ESR_ELx_ExType_SHIFT (20) #define ESR_ELx_ExType_MASK GENMASK(23, 20) #define ESR_ELx_Raddr_SHIFT (10) #define ESR_ELx_Raddr_MASK GENMASK(14, 10) #define ESR_ELx_Rn_SHIFT (5) #define ESR_ELx_Rn_MASK GENMASK(9, 5) #define ESR_ELx_Rvalue_SHIFT 5 #define ESR_ELx_Rvalue_MASK GENMASK(9, 5) #define ESR_ELx_IT_SHIFT (0) #define ESR_ELx_IT_MASK GENMASK(4, 0) #define ESR_ELx_ExType_DATA_CHECK 0 #define ESR_ELx_ExType_EXLOCK 1 #define ESR_ELx_ExType_STR 2 #define ESR_ELx_IT_RET 0 #define ESR_ELx_IT_GCSPOPM 1 #define ESR_ELx_IT_RET_KEYA 2 #define ESR_ELx_IT_RET_KEYB 3 #define ESR_ELx_IT_GCSSS1 4 #define ESR_ELx_IT_GCSSS2 5 #define ESR_ELx_IT_GCSPOPCX 6 #define ESR_ELx_IT_GCSPOPX 7 #ifndef __ASSEMBLY__ #include <asm/types.h> static inline unsigned long esr_brk_comment(unsigned long esr) { return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK; } static inline bool esr_is_data_abort(unsigned long esr) { const unsigned long ec = ESR_ELx_EC(esr); return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; } static inline bool esr_is_cfi_brk(unsigned long esr) { return ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 && (esr_brk_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE; } static inline bool esr_fsc_is_translation_fault(unsigned long esr) { esr = esr & ESR_ELx_FSC; return (esr == ESR_ELx_FSC_FAULT_L(3)) || (esr == ESR_ELx_FSC_FAULT_L(2)) || (esr == ESR_ELx_FSC_FAULT_L(1)) || (esr == ESR_ELx_FSC_FAULT_L(0)) || (esr == ESR_ELx_FSC_FAULT_L(-1)); } static inline bool esr_fsc_is_permission_fault(unsigned long esr) { esr = esr & ESR_ELx_FSC; return (esr == ESR_ELx_FSC_PERM_L(3)) || (esr == ESR_ELx_FSC_PERM_L(2)) || (esr == ESR_ELx_FSC_PERM_L(1)) || (esr == ESR_ELx_FSC_PERM_L(0)); } static inline bool esr_fsc_is_access_flag_fault(unsigned long esr) { esr = esr & ESR_ELx_FSC; return (esr == ESR_ELx_FSC_ACCESS_L(3)) || (esr == ESR_ELx_FSC_ACCESS_L(2)) || (esr == ESR_ELx_FSC_ACCESS_L(1)) || (esr == ESR_ELx_FSC_ACCESS_L(0)); } /* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */ static inline bool esr_iss_is_eretax(unsigned long esr) { return esr & ESR_ELx_ERET_ISS_ERET; } /* Indicate which key is used for ERETAx (false: A-Key, true: B-Key) */ static inline bool esr_iss_is_eretab(unsigned long esr) { return esr & ESR_ELx_ERET_ISS_ERETA; } const char *esr_get_class_string(unsigned long esr); #endif /* __ASSEMBLY */ #endif /* __ASM_ESR_H */
| Name | Type | Size | Permission | Actions |
|---|---|---|---|---|
| stacktrace | Folder | 0755 |
|
|
| vdso | Folder | 0755 |
|
|
| xen | Folder | 0755 |
|
|
| Kbuild | File | 528 B | 0644 |
|
| acenv.h | File | 395 B | 0644 |
|
| acpi.h | File | 5.48 KB | 0644 |
|
| alternative-macros.h | File | 6.45 KB | 0644 |
|
| alternative.h | File | 1.08 KB | 0644 |
|
| apple_m1_pmu.h | File | 2.23 KB | 0644 |
|
| arch_gicv3.h | File | 4.44 KB | 0644 |
|
| arch_timer.h | File | 4.84 KB | 0644 |
|
| archrandom.h | File | 2.99 KB | 0644 |
|
| arm-cci.h | File | 254 B | 0644 |
|
| arm_dsu_pmu.h | File | 2.94 KB | 0644 |
|
| arm_pmuv3.h | File | 3.4 KB | 0644 |
|
| asm-bug.h | File | 952 B | 0644 |
|
| asm-extable.h | File | 3.59 KB | 0644 |
|
| asm-offsets.h | File | 35 B | 0644 |
|
| asm-prototypes.h | File | 958 B | 0644 |
|
| asm-uaccess.h | File | 2.38 KB | 0644 |
|
| asm_pointer_auth.h | File | 2.49 KB | 0644 |
|
| assembler.h | File | 21.19 KB | 0644 |
|
| atomic.h | File | 7.23 KB | 0644 |
|
| atomic_ll_sc.h | File | 10.75 KB | 0644 |
|
| atomic_lse.h | File | 8.2 KB | 0644 |
|
| barrier.h | File | 5.85 KB | 0644 |
|
| bitops.h | File | 813 B | 0644 |
|
| bitrev.h | File | 452 B | 0644 |
|
| boot.h | File | 369 B | 0644 |
|
| brk-imm.h | File | 1.27 KB | 0644 |
|
| bug.h | File | 572 B | 0644 |
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| cache.h | File | 3.28 KB | 0644 |
|
| cacheflush.h | File | 4.61 KB | 0644 |
|
| checksum.h | File | 1.06 KB | 0644 |
|
| clocksource.h | File | 136 B | 0644 |
|
| cmpxchg.h | File | 7.15 KB | 0644 |
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| compat.h | File | 2.13 KB | 0644 |
|
| compiler.h | File | 979 B | 0644 |
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| cpu.h | File | 1.57 KB | 0644 |
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| cpu_ops.h | File | 1.92 KB | 0644 |
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| cpucaps.h | File | 2.28 KB | 0644 |
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| cpufeature.h | File | 32.74 KB | 0644 |
|
| cpuidle.h | File | 1.03 KB | 0644 |
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| cputype.h | File | 13.99 KB | 0644 |
|
| crash_reserve.h | File | 335 B | 0644 |
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| current.h | File | 517 B | 0644 |
|
| daifflags.h | File | 3.45 KB | 0644 |
|
| dcc.h | File | 981 B | 0644 |
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| debug-monitors.h | File | 3.26 KB | 0644 |
|
| device.h | File | 189 B | 0644 |
|
| dmi.h | File | 850 B | 0644 |
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| efi.h | File | 5.05 KB | 0644 |
|
| el2_setup.h | File | 11.6 KB | 0644 |
|
| elf.h | File | 8 KB | 0644 |
|
| esr.h | File | 17.16 KB | 0644 |
|
| exception.h | File | 3.29 KB | 0644 |
|
| exec.h | File | 278 B | 0644 |
|
| extable.h | File | 1.36 KB | 0644 |
|
| fixmap.h | File | 3.11 KB | 0644 |
|
| fpsimd.h | File | 11.63 KB | 0644 |
|
| fpsimdmacros.h | File | 7.7 KB | 0644 |
|
| fpu.h | File | 309 B | 0644 |
|
| ftrace.h | File | 5.93 KB | 0644 |
|
| futex.h | File | 2.71 KB | 0644 |
|
| gcs.h | File | 2.1 KB | 0644 |
|
| gpr-num.h | File | 708 B | 0644 |
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| hardirq.h | File | 2.28 KB | 0644 |
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| hugetlb.h | File | 3.07 KB | 0644 |
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| hw_breakpoint.h | File | 4.16 KB | 0644 |
|
| hwcap.h | File | 8.77 KB | 0644 |
|
| hyp_image.h | File | 1.87 KB | 0644 |
|
| hypervisor.h | File | 444 B | 0644 |
|
| image.h | File | 1.48 KB | 0644 |
|
| insn-def.h | File | 571 B | 0644 |
|
| insn.h | File | 23.8 KB | 0644 |
|
| io.h | File | 8.9 KB | 0644 |
|
| irq.h | File | 571 B | 0644 |
|
| irq_work.h | File | 192 B | 0644 |
|
| irqflags.h | File | 4.31 KB | 0644 |
|
| jump_label.h | File | 1.32 KB | 0644 |
|
| kasan.h | File | 578 B | 0644 |
|
| kernel-pgtable.h | File | 3.3 KB | 0644 |
|
| kexec.h | File | 3.37 KB | 0644 |
|
| kfence.h | File | 680 B | 0644 |
|
| kgdb.h | File | 3.27 KB | 0644 |
|
| kprobes.h | File | 965 B | 0644 |
|
| kvm_arm.h | File | 14.34 KB | 0644 |
|
| kvm_asm.h | File | 12.18 KB | 0644 |
|
| kvm_emulate.h | File | 16.59 KB | 0644 |
|
| kvm_host.h | File | 47.41 KB | 0644 |
|
| kvm_hyp.h | File | 5.14 KB | 0644 |
|
| kvm_mmu.h | File | 11.14 KB | 0644 |
|
| kvm_mte.h | File | 1.35 KB | 0644 |
|
| kvm_nested.h | File | 6.23 KB | 0644 |
|
| kvm_pgtable.h | File | 28.64 KB | 0644 |
|
| kvm_pkvm.h | File | 5.35 KB | 0644 |
|
| kvm_ptrauth.h | File | 4.04 KB | 0644 |
|
| kvm_ras.h | File | 594 B | 0644 |
|
| kvm_types.h | File | 185 B | 0644 |
|
| linkage.h | File | 1.19 KB | 0644 |
|
| lse.h | File | 933 B | 0644 |
|
| mem_encrypt.h | File | 999 B | 0644 |
|
| memory.h | File | 14.24 KB | 0644 |
|
| mman.h | File | 2.36 KB | 0644 |
|
| mmu.h | File | 3.47 KB | 0644 |
|
| mmu_context.h | File | 8.5 KB | 0644 |
|
| module.h | File | 1.73 KB | 0644 |
|
| module.lds.h | File | 795 B | 0644 |
|
| mshyperv.h | File | 1.34 KB | 0644 |
|
| mte-def.h | File | 577 B | 0644 |
|
| mte-kasan.h | File | 5.58 KB | 0644 |
|
| mte.h | File | 6.99 KB | 0644 |
|
| neon-intrinsics.h | File | 959 B | 0644 |
|
| neon.h | File | 385 B | 0644 |
|
| numa.h | File | 165 B | 0644 |
|
| page-def.h | File | 296 B | 0644 |
|
| page.h | File | 1.34 KB | 0644 |
|
| paravirt.h | File | 580 B | 0644 |
|
| paravirt_api_clock.h | File | 26 B | 0644 |
|
| pci.h | File | 469 B | 0644 |
|
| percpu.h | File | 8.31 KB | 0644 |
|
| perf_event.h | File | 515 B | 0644 |
|
| pgalloc.h | File | 3.04 KB | 0644 |
|
| pgtable-hwdef.h | File | 11.47 KB | 0644 |
|
| pgtable-prot.h | File | 8.19 KB | 0644 |
|
| pgtable-types.h | File | 1.41 KB | 0644 |
|
| pgtable.h | File | 52.72 KB | 0644 |
|
| pkeys.h | File | 2.36 KB | 0644 |
|
| pointer_auth.h | File | 4.68 KB | 0644 |
|
| por.h | File | 635 B | 0644 |
|
| preempt.h | File | 2.71 KB | 0644 |
|
| probes.h | File | 549 B | 0644 |
|
| proc-fns.h | File | 562 B | 0644 |
|
| processor.h | File | 12.19 KB | 0644 |
|
| ptdump.h | File | 1.78 KB | 0644 |
|
| ptrace.h | File | 9.35 KB | 0644 |
|
| pvclock-abi.h | File | 374 B | 0644 |
|
| rsi.h | File | 1.64 KB | 0644 |
|
| rsi_cmds.h | File | 3.85 KB | 0644 |
|
| rsi_smc.h | File | 5.23 KB | 0644 |
|
| runtime-const.h | File | 2.3 KB | 0644 |
|
| rwonce.h | File | 1.96 KB | 0644 |
|
| scs.h | File | 1.09 KB | 0644 |
|
| sdei.h | File | 1.53 KB | 0644 |
|
| seccomp.h | File | 891 B | 0644 |
|
| sections.h | File | 1.14 KB | 0644 |
|
| semihost.h | File | 537 B | 0644 |
|
| set_memory.h | File | 715 B | 0644 |
|
| setup.h | File | 789 B | 0644 |
|
| shmparam.h | File | 425 B | 0644 |
|
| signal.h | File | 650 B | 0644 |
|
| signal32.h | File | 1.93 KB | 0644 |
|
| simd.h | File | 1.04 KB | 0644 |
|
| smp.h | File | 3.44 KB | 0644 |
|
| smp_plat.h | File | 824 B | 0644 |
|
| sparsemem.h | File | 747 B | 0644 |
|
| spectre.h | File | 3.75 KB | 0644 |
|
| spinlock.h | File | 601 B | 0644 |
|
| spinlock_types.h | File | 366 B | 0644 |
|
| stack_pointer.h | File | 247 B | 0644 |
|
| stackprotector.h | File | 1.15 KB | 0644 |
|
| stacktrace.h | File | 2.96 KB | 0644 |
|
| stage2_pgtable.h | File | 1.03 KB | 0644 |
|
| stat.h | File | 947 B | 0644 |
|
| string.h | File | 1.89 KB | 0644 |
|
| suspend.h | File | 1.65 KB | 0644 |
|
| sync_bitops.h | File | 1.06 KB | 0644 |
|
| syscall.h | File | 1.97 KB | 0644 |
|
| syscall_wrapper.h | File | 3.09 KB | 0644 |
|
| sysreg.h | File | 46.33 KB | 0644 |
|
| system_misc.h | File | 880 B | 0644 |
|
| text-patching.h | File | 544 B | 0644 |
|
| thread_info.h | File | 3.96 KB | 0644 |
|
| timex.h | File | 343 B | 0644 |
|
| tlb.h | File | 2.65 KB | 0644 |
|
| tlbbatch.h | File | 281 B | 0644 |
|
| tlbflush.h | File | 17.05 KB | 0644 |
|
| topology.h | File | 1.22 KB | 0644 |
|
| trans_pgd.h | File | 1.02 KB | 0644 |
|
| traps.h | File | 4.37 KB | 0644 |
|
| uaccess.h | File | 14.43 KB | 0644 |
|
| unistd.h | File | 898 B | 0644 |
|
| unistd32.h | File | 240 B | 0644 |
|
| uprobes.h | File | 579 B | 0644 |
|
| vdso.h | File | 468 B | 0644 |
|
| vectors.h | File | 1.74 KB | 0644 |
|
| vermagic.h | File | 200 B | 0644 |
|
| virt.h | File | 4.26 KB | 0644 |
|
| vmalloc.h | File | 805 B | 0644 |
|
| vmap_stack.h | File | 739 B | 0644 |
|
| vncr_mapping.h | File | 3.56 KB | 0644 |
|
| word-at-a-time.h | File | 1.5 KB | 0644 |
|
| xor.h | File | 1.88 KB | 0644 |
|